diff --git a/vlsi/Makefile b/vlsi/Makefile
index 0693db7e..339e3c80 100644
--- a/vlsi/Makefile
+++ b/vlsi/Makefile
@@ -122,7 +122,7 @@ $(SYN_CONF): $(VLSI_RTL)
 	echo "synthesis.inputs:" >> $@
 	echo "  top_module: $(VLSI_TOP)" >> $@
 	echo "  input_files:" >> $@
-	for x in $(shell cat $(VLSI_RTL)); do \
+	for x in $$(cat $(VLSI_RTL)); do \
 		echo '    - "'$$x'"' >> $@; \
 	done
 
diff --git a/vlsi/power.mk b/vlsi/power.mk
index bc7359ee..d55b965f 100644
--- a/vlsi/power.mk
+++ b/vlsi/power.mk
@@ -30,7 +30,7 @@ $(POWER_RTL_CONF): $(VLSI_RTL)
 	echo "power.inputs:" >> $@
 	echo "  level: rtl" >> $@
 	echo "  input_files:" >> $@
-	for x in $(shell cat $(VLSI_RTL)); do \
+	for x in $$(cat $(VLSI_RTL)); do \
 		echo '    - "'$$x'"' >> $@; \
 	done
 
diff --git a/vlsi/sim.mk b/vlsi/sim.mk
index 65b836cc..5623f9d3 100644
--- a/vlsi/sim.mk
+++ b/vlsi/sim.mk
@@ -10,7 +10,7 @@ $(SIM_CONF): $(sim_common_files)
 	echo "  top_module: $(VLSI_TOP)" >> $@
 	echo "  tb_name: ''" >> $@  # don't specify -top
 	echo "  input_files:" >> $@
-	for x in $(shell cat $(sim_common_files)); do \
+	for x in $$(cat $(sim_common_files)); do \
 		echo '    - "'$$x'"' >> $@; \
 	done
 	echo "  input_files_meta: 'append'" >> $@