Bump testchipip

fpga/Makefile

@@ -44,20 +44,6 @@ ifeq ($(SUB_PROJECT),vcu118)
 	FPGA_BRAND        ?= xilinx
 endif
 
-ifeq ($(SUB_PROJECT),bringup)
-	SBT_PROJECT       ?= fpga_platforms
-	MODEL             ?= BringupVCU118FPGATestHarness
-	VLOG_MODEL        ?= BringupVCU118FPGATestHarness
-	MODEL_PACKAGE     ?= chipyard.fpga.vcu118.bringup
-	CONFIG            ?= RocketBringupConfig
-	CONFIG_PACKAGE    ?= chipyard.fpga.vcu118.bringup
-	GENERATOR_PACKAGE ?= chipyard
-	TB                ?= none # unused
-	TOP               ?= ChipTop
-	BOARD             ?= vcu118
-	FPGA_BRAND        ?= xilinx
-endif
-
 ifeq ($(SUB_PROJECT),nexysvideo)
 	SBT_PROJECT       ?= fpga_platforms
 	MODEL             ?= NexysVideoHarness

generators/chipyard/src/main/scala/harness/HarnessBinders.scala

@@ -213,8 +213,7 @@ class WithSerialTLTiedOff(tieoffs: Option[Seq[Int]] = None) extends HarnessBinde
       case io: SourceSyncPhitIO => {
         io.clock_in := false.B.asClock
         io.reset_in := false.B.asAsyncReset
-        io.phit_in := DontCare
+        io.in := DontCare
-        io.credit_in := DontCare
       }
     }
     port.io match {

generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala

@@ -69,10 +69,8 @@ class WithMultiChipSerialTL(chip0: Int, chip1: Int, chip0portId: Int = 0, chip1p
       b.clock_in := a.clock_out
       a.reset_in := b.reset_out
       b.reset_in := a.reset_out
-      a.phit_in := b.phit_out
+      a.in := b.out
-      b.phit_in := a.phit_out
+      b.in := a.out
-      a.credit_in := b.credit_out
-      b.credit_in := a.credit_out
     }
     (p0.io, p1.io) match {
       case (io0: InternalSyncPhitIO, io1: ExternalSyncPhitIO) => connectDecoupledSyncPhitIO(io0, io1)