merge the different ExampleTop subclasses into the example package

src/main/scala/example/Configs.scala

@@ -1,14 +1,56 @@
 package example
 
+import chisel3._
 import config.{Parameters, Config}
-import testchipip.WithSerialAdapter
+import diplomacy.LazyModule
 import coreplex.WithRoccExample
 import rocketchip.WithoutTLMonitors
+import testchipip._
 
-class DefaultExampleConfig extends Config(
+class WithExampleTop extends Config((site, here, up) => {
+  case BuildTop => (p: Parameters) =>
+    Module(LazyModule(new ExampleTop()(p)).module)
+})
+
+class WithPWM extends Config((site, here, up) => {
+  case BuildTop => (p: Parameters) =>
+    Module(LazyModule(new ExampleTopWithPWM()(p)).module)
+})
+
+class WithBlockDeviceModel extends Config((site, here, up) => {
+  case BuildTop => (p: Parameters) => {
+    val top = Module(LazyModule(new ExampleTopWithBlockDevice()(p)).module)
+    top.connectBlockDeviceModel()
+    top
+  }
+})
+
+class WithSimBlockDevice extends Config((site, here, up) => {
+  case BuildTop => (p: Parameters) => {
+    val top = Module(LazyModule(new ExampleTopWithBlockDevice()(p)).module)
+    top.connectSimBlockDevice()
+    top
+  }
+})
+
+class BaseExampleConfig extends Config(
   new WithoutTLMonitors ++
   new WithSerialAdapter ++
   new rocketchip.DefaultConfig)
 
+class DefaultExampleConfig extends Config(
+  new WithExampleTop ++ new BaseExampleConfig)
+
 class RoccExampleConfig extends Config(
   new WithRoccExample ++ new DefaultExampleConfig)
+
+class PWMConfig extends Config(new WithPWM ++ new BaseExampleConfig)
+
+class SimBlockDeviceConfig extends Config(
+  new WithBlockDevice ++ new WithSimBlockDevice ++ new BaseExampleConfig)
+
+class BlockDeviceModelConfig extends Config(
+  new WithBlockDevice ++ new WithBlockDeviceModel ++ new BaseExampleConfig)
+
+class WithTwoTrackers extends WithNBlockDeviceTrackers(2)
+class WithFourTrackers extends WithNBlockDeviceTrackers(4)

src/main/scala/example/PWM.scala

@@ -0,0 +1,98 @@
+package example
+
+import chisel3._
+import chisel3.util._
+import config.{Parameters, Field}
+import uncore.tilelink._
+import uncore.tilelink2._
+import junctions._
+import diplomacy._
+import regmapper.{HasRegMap, RegField}
+import rocketchip._
+import _root_.util.UIntIsOneOf
+
+case class PWMParams(address: BigInt, beatBytes: Int)
+
+class PWMBase(w: Int) extends Module {
+  val io = IO(new Bundle {
+    val pwmout = Output(Bool())
+    val period = Input(UInt(w.W))
+    val duty = Input(UInt(w.W))
+    val enable = Input(Bool())
+  })
+
+  // The counter should count up until period is reached
+  val counter = Reg(UInt(w.W))
+
+  when (counter >= (io.period - 1.U)) {
+    counter := 0.U
+  } .otherwise {
+    counter := counter + 1.U
+  }
+
+  // If PWM is enabled, pwmout is high when counter < duty
+  // If PWM is not enabled, it will always be low
+  io.pwmout := io.enable && (counter < io.duty)
+}
+
+trait PWMTLBundle extends Bundle {
+  val pwmout = Output(Bool())
+}
+
+trait PWMTLModule extends Module with HasRegMap {
+  val io: PWMTLBundle
+  implicit val p: Parameters
+  def params: PWMParams
+
+  val w = params.beatBytes * 8
+  require(w <= 32)
+
+  // How many clock cycles in a PWM cycle?
+  val period = Reg(UInt(w.W))
+  // For how many cycles should the clock be high?
+  val duty = Reg(UInt(w.W))
+  // Is the PWM even running at all?
+  val enable = RegInit(false.B)
+
+  val base = Module(new PWMBase(w))
+  io.pwmout := base.io.pwmout
+  base.io.period := period
+  base.io.duty := duty
+  base.io.enable := enable
+
+  regmap(
+    0x00 -> Seq(
+      RegField(w, period)),
+    0x04 -> Seq(
+      RegField(w, duty)),
+    0x08 -> Seq(
+      RegField(1, enable)))
+}
+
+class PWMTL(c: PWMParams)(implicit p: Parameters)
+  extends TLRegisterRouter(
+    c.address, "pwm", Seq("ucbbar,pwm"),
+    beatBytes = c.beatBytes)(
+      new TLRegBundle(c, _) with PWMTLBundle)(
+      new TLRegModule(c, _, _) with PWMTLModule)
+
+trait HasPeripheryPWM extends HasSystemNetworks {
+  implicit val p: Parameters
+
+  private val address = 0x2000
+
+  val pwm = LazyModule(new PWMTL(
+    PWMParams(address, peripheryBusConfig.beatBytes))(p))
+
+  pwm.node := TLFragmenter(
+    peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
+}
+
+trait HasPeripheryPWMModuleImp extends LazyMultiIOModuleImp {
+  implicit val p: Parameters
+  val outer: HasPeripheryPWM
+
+  val pwmout = IO(Output(Bool()))
+
+  pwmout := outer.pwm.module.io.pwmout
+}

src/main/scala/example/TestHarness.scala

@@ -4,16 +4,16 @@ import diplomacy.LazyModule
 import rocketchip._
 import testchipip._
 import chisel3._
-import config.Parameters
+import config.{Field, Parameters}
+
+case object BuildTop extends Field[Parameters => ExampleTopModule[ExampleTop]]
 
 class TestHarness(implicit val p: Parameters) extends Module {
   val io = IO(new Bundle {
     val success = Output(Bool())
   })
 
-  def buildTop(p: Parameters): ExampleTop = LazyModule(new ExampleTop()(p))
-
-  val dut = Module(buildTop(p).module)
+  val dut = p(BuildTop)(p)
   dut.connectSimAXIMem()
   io.success := dut.connectSimSerial()
 }

src/main/scala/example/Top.scala

@@ -24,3 +24,20 @@ class ExampleTopModule[+L <: ExampleTop](l: L) extends BaseSystemModule(l)
     with HasRocketPlexMasterModuleImp
     with HasNoDebugModuleImp
     with HasPeripherySerialModuleImp
+
+class ExampleTopWithPWM(implicit p: Parameters) extends ExampleTop
+    with HasPeripheryPWM {
+  override lazy val module = new ExampleTopWithPWMModule(this)
+}
+
+class ExampleTopWithPWMModule(l: ExampleTopWithPWM)
+  extends ExampleTopModule(l) with HasPeripheryPWMModuleImp
+
+class ExampleTopWithBlockDevice(implicit p: Parameters) extends ExampleTop
+    with HasPeripheryBlockDevice {
+  override lazy val module = new ExampleTopWithBlockDeviceModule(this)
+}
+
+class ExampleTopWithBlockDeviceModule(l: ExampleTopWithBlockDevice)
+  extends ExampleTopModule(l)
+  with HasPeripheryBlockDeviceModuleImp