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Add TestChipConfigTweaks to model 2/1 tile/uncore division

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This commit is contained in:
Jerry Zhao
2023-05-26 11:56:58 -07:00
parent 26a6f62ca7
commit f73951ac7f
1 changed files with 16 additions and 0 deletions
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16
generators/firechip/src/main/scala/TargetConfigs.scala
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@@ -164,6 +164,22 @@ class WithFireSimHighPerfConfigTweaks extends Config(
new WithFireSimDesignTweaks
)
// Tweak more representative of testchip configs
class WithFireSimTestChipConfigTweaks extends Config(
// Frequency specifications
new chipyard.config.WithTileFrequency(1000.0) ++ // Realistic tile frequency for a test chip
new chipyard.config.WithSystemBusFrequency(500.0) ++ // Realistic system bus frequency
new chipyard.config.WithMemoryBusFrequency(1000.0) ++ // Needs to be 1000 MHz to model DDR performance accurately
new chipyard.config.WithPeripheryBusFrequency(500.0) ++ // Match the sbus and pbus frequency
// Crossing specifications
new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS
new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS
new freechips.rocketchip.subsystem.WithRationalRocketTiles ++ // Add rational crossings between RocketTile and uncore
new boom.common.WithRationalBoomTiles ++ // Add rational crossings between BoomTile and uncore
new testchipip.WithAsynchronousSerialSlaveCrossing ++ // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS
new WithFireSimDesignTweaks
)
/*******************************************************************************
* Full TARGET_CONFIG configurations. These set parameters of the target being
* simulated.