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Pass base of memory to SimDRAM

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This commit is contained in:
Jerry Zhao
2023-04-12 01:37:05 -07:00
parent e51b3e8c61
commit f5ceab2077
2 changed files with 7 additions and 3 deletions
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7
generators/chipyard/src/main/scala/HarnessBinders.scala
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@@ -168,8 +168,9 @@ class WithSimAXIMemOverSerialTL extends OverrideHarnessBinder({
// connect SimDRAM from the AXI port coming from the harness multi clock axi ram // connect SimDRAM from the AXI port coming from the harness multi clock axi ram
(harnessMultiClockAXIRAM.mem_axi4 zip harnessMultiClockAXIRAM.memNode.edges.in).map { case (axi_port, edge) => (harnessMultiClockAXIRAM.mem_axi4 zip harnessMultiClockAXIRAM.memNode.edges.in).map { case (axi_port, edge) =>
val memSize = sVal.memParams.size val memSize = sVal.memParams.size
val memBase = sVal.memParams.base
val lineSize = p(CacheBlockBytes) val lineSize = p(CacheBlockBytes)
val mem = Module(new SimDRAM(memSize, lineSize, BigInt(memFreq.toLong), edge.bundle)).suggestName("simdram") val mem = Module(new SimDRAM(memSize, lineSize, BigInt(memFreq.toLong), memBase, edge.bundle)).suggestName("simdram")
mem.io.axi <> axi_port.bits mem.io.axi <> axi_port.bits
mem.io.clock := axi_port.clock mem.io.clock := axi_port.clock
mem.io.reset := axi_port.reset mem.io.reset := axi_port.reset
@@ -184,10 +185,12 @@ class WithBlackBoxSimMem(additionalLatency: Int = 0) extends OverrideHarnessBind
(system: CanHaveMasterAXI4MemPort, th: HasHarnessSignalReferences, ports: Seq[ClockedAndResetIO[AXI4Bundle]]) => { (system: CanHaveMasterAXI4MemPort, th: HasHarnessSignalReferences, ports: Seq[ClockedAndResetIO[AXI4Bundle]]) => {
val p: Parameters = chipyard.iobinders.GetSystemParameters(system) val p: Parameters = chipyard.iobinders.GetSystemParameters(system)
(ports zip system.memAXI4Node.edges.in).map { case (port, edge) => (ports zip system.memAXI4Node.edges.in).map { case (port, edge) =>
// TODO FIX: This currently makes each SimDRAM contian the entire memory space
val memSize = p(ExtMem).get.master.size val memSize = p(ExtMem).get.master.size
val memBase = p(ExtMem).get.master.base
val lineSize = p(CacheBlockBytes) val lineSize = p(CacheBlockBytes)
val clockFreq = p(MemoryBusKey).dtsFrequency.get val clockFreq = p(MemoryBusKey).dtsFrequency.get
val mem = Module(new SimDRAM(memSize, lineSize, clockFreq, edge.bundle)).suggestName("simdram") val mem = Module(new SimDRAM(memSize, lineSize, clockFreq, memBase, edge.bundle)).suggestName("simdram")
mem.io.axi <> port.bits mem.io.axi <> port.bits
// Bug in Chisel implementation. See https://github.com/chipsalliance/chisel3/pull/1781 // Bug in Chisel implementation. See https://github.com/chipsalliance/chisel3/pull/1781
def Decoupled[T <: Data](irr: IrrevocableIO[T]): DecoupledIO[T] = { def Decoupled[T <: Data](irr: IrrevocableIO[T]): DecoupledIO[T] = {

3
generators/chipyard/src/main/scala/example/FlatTestHarness.scala
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@@ -60,8 +60,9 @@ class FlatTestHarness(implicit val p: Parameters) extends Module {
// connect SimDRAM from the AXI port coming from the harness multi clock axi ram // connect SimDRAM from the AXI port coming from the harness multi clock axi ram
(harnessMultiClockAXIRAM.mem_axi4 zip harnessMultiClockAXIRAM.memNode.edges.in).map { case (axi_port, edge) => (harnessMultiClockAXIRAM.mem_axi4 zip harnessMultiClockAXIRAM.memNode.edges.in).map { case (axi_port, edge) =>
val memSize = sVal.memParams.size val memSize = sVal.memParams.size
val memBase = sVal.memParams.base
val lineSize = p(CacheBlockBytes) val lineSize = p(CacheBlockBytes)
val mem = Module(new SimDRAM(memSize, lineSize, BigInt(memFreq.toLong), edge.bundle)).suggestName("simdram") val mem = Module(new SimDRAM(memSize, lineSize, BigInt(memFreq.toLong), memBase, edge.bundle)).suggestName("simdram")
mem.io.axi <> axi_port.bits mem.io.axi <> axi_port.bits
mem.io.clock := axi_port.clock mem.io.clock := axi_port.clock
mem.io.reset := axi_port.reset mem.io.reset := axi_port.reset