wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Merge remote-tracking branch 'origin/dev' into HEAD

Browse Source
This commit is contained in:
Paul Rigge
2020-05-23 22:49:51 +00:00
parent 0cc643bfdb c2c9bc83de
commit f56e367d59
101 changed files with 8537 additions and 708 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
tests/.gitignore vendored
View File

@@ -1,4 +1,5 @@
*.o
*.riscv
*.dump
*.img
libgloss/

10
tests/Makefile
View File

@@ -5,12 +5,16 @@ LDFLAGS= -static
include libgloss.mk
PROGRAMS = pwm blkdev accum charcount nic-loopback big-blkdev pingd passthrough fir
PROGRAMS = pwm blkdev accum charcount nic-loopback big-blkdev pingd \
passthrough fir nvdla spiflashread spiflashwrite
spiflash.img: spiflash.py
python3 $<
.DEFAULT_GOAL := default
.PHONY: default
default: $(addsuffix .riscv,$(PROGRAMS))
default: $(addsuffix .riscv,$(PROGRAMS)) spiflash.img
.PHONY: dumps
dumps: $(addsuffix .dump,$(PROGRAMS))
@@ -18,7 +22,7 @@ dumps: $(addsuffix .dump,$(PROGRAMS))
%.o: %.S
$(GCC) $(CFLAGS) -D__ASSEMBLY__=1 -c $< -o $@
%.o: %.c mmio.h
%.o: %.c mmio.h spiflash.h
$(GCC) $(CFLAGS) -c $< -o $@
%.riscv: %.o $(libgloss)

468
tests/nvdla.c Normal file
View File

@@ -0,0 +1,468 @@
#include <stdint.h>
#include "nvdla.h"
#include "mmio.h"
#include <riscv-pk/encoding.h>
#define NVDLA_BASE 0x10040000
#define reg_write(addr,val) reg_write32(NVDLA_BASE+addr,val)
#define reg_read(addr) reg_read32(NVDLA_BASE+addr)
int main(void)
{
//----------## Layer:CDP_0: cross layer dependency, begin----------
//----------## Layer:CDP_0: cross layer dependency, end----------
//----------## Layer:CDP_0: set producer pointer, begin----------
reg_write(CDP_S_POINTER_0, 0);
reg_write(CDP_RDMA_S_POINTER_0, 0);
//----------## Layer:CDP_0: set producer pointer, end----------
//----------## Layer:CDP_0: LUT programming, begin----------
reg_write(CDP_S_LUT_ACCESS_CFG_0, 0x30000);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x0);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x1);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x2);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x3);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x4);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x5);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x6);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x7);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x8);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x9);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xa);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xb);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xc);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xd);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xe);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xf);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x10);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x11);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x12);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x13);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x14);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x15);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x16);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x17);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x18);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x19);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x1a);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x1b);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x1c);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x1d);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x1e);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x1f);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x20);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x21);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x22);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x23);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x24);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x25);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x26);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x27);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x28);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x29);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x2a);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x2b);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x2c);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x2d);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x2e);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x2f);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x30);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x31);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x32);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x33);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x34);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x35);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x36);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x37);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x38);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x39);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x3a);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x3b);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x3c);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x3d);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x3e);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x3f);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x40);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x41);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x42);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x43);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x44);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x45);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x46);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x47);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x48);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x49);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x4a);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x4b);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x4c);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x4d);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x4e);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x4f);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x50);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x51);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x52);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x53);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x54);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x55);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x56);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x57);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x58);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x59);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x5a);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x5b);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x5c);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x5d);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x5e);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x5f);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x60);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x61);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x62);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x63);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x64);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x65);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x66);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x67);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x68);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x69);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x6a);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x6b);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x6c);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x6d);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x6e);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x6f);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x70);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x71);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x72);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x73);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x74);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x75);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x76);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x77);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x78);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x79);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x7a);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x7b);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x7c);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x7d);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x7e);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x7f);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x80);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x81);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x82);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x83);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x84);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x85);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x86);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x87);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x88);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x89);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x8a);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x8b);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x8c);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x8d);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x8e);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x8f);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x90);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x91);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x92);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x93);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x94);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x95);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x96);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x97);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x98);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x99);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x9a);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x9b);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x9c);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x9d);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x9e);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x9f);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xa0);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xa1);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xa2);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xa3);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xa4);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xa5);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xa6);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xa7);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xa8);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xa9);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xaa);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xab);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xac);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xad);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xae);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xaf);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xb0);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xb1);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xb2);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xb3);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xb4);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xb5);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xb6);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xb7);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xb8);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xb9);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xba);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xbb);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xbc);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xbd);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xbe);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xbf);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xc0);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xc1);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xc2);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xc3);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xc4);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xc5);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xc6);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xc7);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xc8);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xc9);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xca);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xcb);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xcc);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xcd);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xce);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xcf);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xd0);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xd1);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xd2);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xd3);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xd4);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xd5);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xd6);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xd7);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xd8);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xd9);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xda);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xdb);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xdc);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xdd);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xde);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xdf);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xe0);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xe1);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xe2);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xe3);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xe4);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xe5);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xe6);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xe7);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xe8);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xe9);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xea);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xeb);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xec);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xed);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xee);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xef);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xf0);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xf1);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xf2);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xf3);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xf4);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xf5);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xf6);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xf7);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xf8);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xf9);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xfa);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xfb);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xfc);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xfd);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xfe);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xff);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x100);
reg_write(CDP_S_LUT_ACCESS_CFG_0, 0x20000);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x0);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x1);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x2);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x3);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x4);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x5);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x6);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x7);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x8);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x9);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xa);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xb);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xc);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xd);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xe);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xf);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x10);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x11);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x12);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x13);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x14);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x15);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x16);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x17);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x18);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x19);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x1a);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x1b);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x1c);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x1d);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x1e);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x1f);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x20);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x21);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x22);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x23);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x24);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x25);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x26);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x27);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x28);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x29);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x2a);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x2b);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x2c);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x2d);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x2e);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x2f);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x30);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x31);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x32);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x33);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x34);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x35);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x36);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x37);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x38);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x39);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x3a);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x3b);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x3c);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x3d);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x3e);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x3f);
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x40);
reg_write(CDP_S_LUT_LE_START_LOW_0, 0x0);
// CDP_S_LUT_LE_START_LOW_0.LUT_LE_START_LOW:0x0
reg_write(CDP_S_LUT_LO_END_LOW_0, 0x100);
// CDP_S_LUT_LO_END_LOW_0.LUT_LO_END_LOW:0x100
reg_write(CDP_S_LUT_ACCESS_CFG_0, 0x0);
// CDP_S_LUT_ACCESS_CFG_0.LUT_ACCESS_TYPE:READ : 0x0
// CDP_S_LUT_ACCESS_CFG_0.LUT_TABLE_ID:LE : 0x0
// CDP_S_LUT_ACCESS_CFG_0.LUT_ADDR:0x0
reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x0);
// CDP_S_LUT_ACCESS_DATA_0.LUT_DATA:0x0
reg_write(CDP_S_LUT_LE_START_HIGH_0, 0x0);
// CDP_S_LUT_LE_START_HIGH_0.LUT_LE_START_HIGH:0x0
reg_write(CDP_S_LUT_LO_END_HIGH_0, 0x0);
// CDP_S_LUT_LO_END_HIGH_0.LUT_LO_END_HIGH:0x0
reg_write(CDP_S_LUT_CFG_0, 0x1);
// CDP_S_LUT_CFG_0.LUT_UFLOW_PRIORITY:LE : 0x0
// CDP_S_LUT_CFG_0.LUT_OFLOW_PRIORITY:LE : 0x0
// CDP_S_LUT_CFG_0.LUT_HYBRID_PRIORITY:LE : 0x0
// CDP_S_LUT_CFG_0.LUT_LE_FUNCTION:LINEAR : 0x1
reg_write(CDP_S_LUT_LE_SLOPE_SHIFT_0, 0x0);
// CDP_S_LUT_LE_SLOPE_SHIFT_0.LUT_LE_SLOPE_OFLOW_SHIFT:0x0
// CDP_S_LUT_LE_SLOPE_SHIFT_0.LUT_LE_SLOPE_UFLOW_SHIFT:0x0
reg_write(CDP_S_LUT_LE_SLOPE_SCALE_0, 0x0);
// CDP_S_LUT_LE_SLOPE_SCALE_0.LUT_LE_SLOPE_UFLOW_SCALE:0x0
// CDP_S_LUT_LE_SLOPE_SCALE_0.LUT_LE_SLOPE_OFLOW_SCALE:0x0
reg_write(CDP_S_LUT_INFO_0, 0x0);
// CDP_S_LUT_INFO_0.LUT_LE_INDEX_SELECT:0x0
// CDP_S_LUT_INFO_0.LUT_LE_INDEX_OFFSET:0x0
// CDP_S_LUT_INFO_0.LUT_LO_INDEX_SELECT:0x0
reg_write(CDP_S_LUT_LE_END_LOW_0, 0x40);
// CDP_S_LUT_LE_END_LOW_0.LUT_LE_END_LOW:0x40
reg_write(CDP_S_LUT_LO_SLOPE_SCALE_0, 0x0);
// CDP_S_LUT_LO_SLOPE_SCALE_0.LUT_LO_SLOPE_OFLOW_SCALE:0x0
// CDP_S_LUT_LO_SLOPE_SCALE_0.LUT_LO_SLOPE_UFLOW_SCALE:0x0
reg_write(CDP_S_LUT_LE_END_HIGH_0, 0x0);
// CDP_S_LUT_LE_END_HIGH_0.LUT_LE_END_HIGH:0x0
reg_write(CDP_S_LUT_LO_START_HIGH_0, 0x0);
// CDP_S_LUT_LO_START_HIGH_0.LUT_LO_START_HIGH:0x0
reg_write(CDP_S_LUT_LO_START_LOW_0, 0x0);
// CDP_S_LUT_LO_START_LOW_0.LUT_LO_START_LOW:0x0
reg_write(CDP_S_LUT_LO_SLOPE_SHIFT_0, 0x0);
// CDP_S_LUT_LO_SLOPE_SHIFT_0.LUT_LO_SLOPE_UFLOW_SHIFT:0x0
// CDP_S_LUT_LO_SLOPE_SHIFT_0.LUT_LO_SLOPE_OFLOW_SHIFT:0x0
//----------## Layer:CDP_0: LUT programming, end----------
//----------## Layer:CDP_0: configuraion, begin----------
reg_write(CDP_D_DATOUT_OFFSET_0, 0x80);
// CDP_D_DATOUT_OFFSET_0.DATOUT_OFFSET:0x80
reg_write(CDP_D_DST_SURFACE_STRIDE_0, 0x800);
// CDP_D_DST_SURFACE_STRIDE_0.DST_SURFACE_STRIDE:0x40
reg_write(CDP_RDMA_D_SRC_BASE_ADDR_LOW_0, 0x90000000);
// CDP_RDMA_D_SRC_BASE_ADDR_LOW_0.SRC_BASE_ADDR_LOW:0x4000000
reg_write(CDP_D_DST_DMA_CFG_0, 0x1);
// CDP_D_DST_DMA_CFG_0.DST_RAM_TYPE:MC : 0x1
reg_write(CDP_RDMA_D_DATA_CUBE_WIDTH_0, 0x7);
// CDP_RDMA_D_DATA_CUBE_WIDTH_0.WIDTH:0x7
reg_write(CDP_RDMA_D_DATA_FORMAT_0, 0x0);
// CDP_RDMA_D_DATA_FORMAT_0.INPUT_DATA:INT8 : 0x0
reg_write(CDP_D_DATIN_SCALE_0, 0x1);
// CDP_D_DATIN_SCALE_0.DATIN_SCALE:0x1
reg_write(CDP_D_DATOUT_SHIFTER_0, 0x0);
// CDP_D_DATOUT_SHIFTER_0.DATOUT_SHIFTER:0x0
reg_write(CDP_D_CYA_0, 0x0);
// CDP_D_CYA_0.CYA:0x0
reg_write(CDP_RDMA_D_PERF_ENABLE_0, 0x0);
// CDP_RDMA_D_PERF_ENABLE_0.DMA_EN:DISABLE : 0x0
reg_write(CDP_D_LRN_CFG_0, 0x0);
// CDP_D_LRN_CFG_0.NORMALZ_LEN:LEN3 : 0x0
reg_write(CDP_RDMA_D_DATA_CUBE_CHANNEL_0, 0x1f);
// CDP_RDMA_D_DATA_CUBE_CHANNEL_0.CHANNEL:0x1f
reg_write(CDP_D_DATA_FORMAT_0, 0x0);
// CDP_D_DATA_FORMAT_0.INPUT_DATA_TYPE:INT8 : 0x0
reg_write(CDP_D_DATIN_SHIFTER_0, 0x0);
// CDP_D_DATIN_SHIFTER_0.DATIN_SHIFTER:0x0
reg_write(CDP_D_PERF_ENABLE_0, 0x0);
// CDP_D_PERF_ENABLE_0.LUT_EN:DISABLE : 0x0
// CDP_D_PERF_ENABLE_0.DMA_EN:DISABLE : 0x0
reg_write(CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0, 0x0);
// CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0.SRC_BASE_ADDR_HIGH:0x0
reg_write(CDP_D_DST_BASE_ADDR_HIGH_0, 0x0);
// CDP_D_DST_BASE_ADDR_HIGH_0.DST_BASE_ADDR_HIGH:0x0
reg_write(CDP_RDMA_D_SRC_DMA_CFG_0, 0x1);
// CDP_RDMA_D_SRC_DMA_CFG_0.SRC_RAM_TYPE:MC : 0x1
reg_write(CDP_D_DATOUT_SCALE_0, 0x1);
// CDP_D_DATOUT_SCALE_0.DATOUT_SCALE:0x1
reg_write(CDP_D_DATIN_OFFSET_0, 0x80);
// CDP_D_DATIN_OFFSET_0.DATIN_OFFSET:0x80
reg_write(CDP_D_NAN_FLUSH_TO_ZERO_0, 0x0);
// CDP_D_NAN_FLUSH_TO_ZERO_0.NAN_TO_ZERO:DISABLE : 0x0
reg_write(CDP_D_FUNC_BYPASS_0, 0x3);
// CDP_D_FUNC_BYPASS_0.SQSUM_BYPASS:ENABLE : 0x1
// CDP_D_FUNC_BYPASS_0.MUL_BYPASS:ENABLE : 0x1
reg_write(CDP_D_DST_BASE_ADDR_LOW_0, 0x90080000);
// CDP_D_DST_BASE_ADDR_LOW_0.DST_BASE_ADDR_LOW:0x4004000
reg_write(CDP_RDMA_D_CYA_0, 0x0);
// CDP_RDMA_D_CYA_0.CYA:0x0
reg_write(CDP_RDMA_D_SRC_SURFACE_STRIDE_0, 0x800);
// CDP_RDMA_D_SRC_SURFACE_STRIDE_0.SRC_SURFACE_STRIDE:0x40
reg_write(CDP_D_DST_LINE_STRIDE_0, 0x100);
// CDP_D_DST_LINE_STRIDE_0.DST_LINE_STRIDE:0x8
reg_write(CDP_RDMA_D_SRC_LINE_STRIDE_0, 0x100);
// CDP_RDMA_D_SRC_LINE_STRIDE_0.SRC_LINE_STRIDE:0x8
reg_write(CDP_RDMA_D_DATA_CUBE_HEIGHT_0, 0x7);
// CDP_RDMA_D_DATA_CUBE_HEIGHT_0.HEIGHT:0x7
//----------## Layer:CDP_0: configuraion, end----------
//----------## Layer:CDP_0: operation enable, begin----------
//----------#### Layer:CDP_0: operation enable, block:NVDLA_CDP_RDMA, begin --
reg_write(CDP_RDMA_D_OP_ENABLE_0,0x1);
//----------#### Layer:CDP_0: operation enable, block:NVDLA_CDP_RDMA, end --
//----------#### Layer:CDP_0: operation enable, block:NVDLA_CDP, begin --
reg_write(CDP_D_OP_ENABLE_0,0x1);
//----------#### Layer:CDP_0: operation enable, block:NVDLA_CDP, end --
//----------## Layer:CDP_0: operation enable, end----------
register uint64_t cycle1 = rdcycle();
for (register int idx = 0; idx < 32767; idx++) {
if (reg_read(GLB_S_INTR_STATUS_0) != 0)
break;
}
uint64_t cycle2 = rdcycle();
printf("cycle1: %lu, cycle2: %lu, diff: %lu\n", cycle1, cycle2, cycle2 - cycle1 );
return 0;
}

6433
tests/nvdla.h Normal file
View File

File diff suppressed because it is too large Load Diff

174
tests/spiflash.h Normal file
View File

@@ -0,0 +1,174 @@
#ifndef __SPIFLASH_H__
#define __SPIFLASH_H__
// These are configuration-dependent, but for the unit test we'll use the example config
#define SPIFLASH_BASE_MEM 0x20000000
#define SPIFLASH_BASE_MEM_SIZE 0x10000000
#define SPIFLASH_BASE_CTRL 0x10040000
// Only defining the registers we use; there are more
// Software control
#define SPIFLASH_OFFS_CSMODE 0x18
#define SPIFLASH_OFFS_FMT 0x40
#define SPIFLASH_OFFS_TXDATA 0x48
#define SPIFLASH_OFFS_RXDATA 0x4c
// Hardware state machine control
#define SPIFLASH_OFFS_FLASH_EN 0x60
#define SPIFLASH_OFFS_FFMT 0x64
// chip select modes
#define CSMODE_AUTO 0
#define CSMODE_HOLD 2
#define CSMODE_OFF 3
// SPI flash protocol settings
#define SPIFLASH_PROTO_SINGLE 0
#define SPIFLASH_PROTO_DUAL 1
#define SPIFLASH_PROTO_QUAD 2
// SPI flash IO settings
#define SPIFLASH_IODIR_RX 0
#define SPIFLASH_IODIR_TX 1
// SPI flash endianness settings
#define SPIFLASH_ENDIAN_MSB 0
#define SPIFLASH_ENDIAN_LSB 1
static uint8_t test_data[] = {0x13,0x37,0x00,0xff,0xaa,0x55,0xfa,0xce,0x0f,0xf0,0x01,0x23,0x45,0x67,0x89,0xab,0xcd,0xef};
static uint8_t test_len = 16;
typedef union
{
struct {
unsigned int proto : 2;
unsigned int endian : 1;
unsigned int iodir : 1;
unsigned int : 12;
unsigned int len : 4;
unsigned int : 12;
} fields;
uint32_t bits;
} spi_fmt;
typedef union
{
struct {
unsigned int cmd_en : 1;
unsigned int addr_len : 3;
unsigned int pad_cnt : 4;
unsigned int cmd_proto : 2;
unsigned int addr_proto : 2;
unsigned int data_proto : 2;
unsigned int : 2;
unsigned int cmd_code : 8;
unsigned int pad_code : 8;
} fields;
uint32_t bits;
} spiflash_ffmt;
// send something to the SPI TX
void spi_data_write(uint8_t data)
{
while (reg_read32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_TXDATA) >= 0x80000000);
reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_TXDATA, (uint32_t)data);
}
// configure the hardware flash controller
void configure_spiflash(spiflash_ffmt data)
{
reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_FLASH_EN, 0);
reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_FFMT, data.bits);
reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_FLASH_EN, 1);
}
// write some data to the flash using software (there is no hardware write controller)
void write_spiflash(uint8_t *data, uint32_t len, uint32_t addr, uint8_t cmd, uint8_t abytes, uint8_t aproto, uint8_t dproto)
{
spi_fmt fmt;
fmt.fields.proto = SPIFLASH_PROTO_SINGLE;
fmt.fields.endian = SPIFLASH_ENDIAN_MSB;
fmt.fields.iodir = SPIFLASH_IODIR_TX;
fmt.fields.len = 8;
uint32_t i;
// Need to be out of flash mode
reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_FLASH_EN, 0);
reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_FMT, fmt.bits);
reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_CSMODE, CSMODE_HOLD);
spi_data_write(cmd);
// need to wait a bit to flush the tx queue before changing fmt
for(i = 0; i < 0x100; i++) asm volatile ("nop");
fmt.fields.proto = aproto;
reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_FMT, fmt.bits);
for (i = abytes; i > 0; i--)
{
spi_data_write((uint8_t)(addr >> (i*8-8)));
}
// need to wait a bit to flush the tx queue before changing fmt
for(i = 0; i < 0x100; i++) asm volatile ("nop");
fmt.fields.proto = dproto;
reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_FMT, fmt.bits);
for (i = 0; i < len; i++)
{
spi_data_write(data[i]);
}
// need to wait a bit to flush the tx queue before deasserting CS
for(i = 0; i < 0x100; i++) asm volatile ("nop");
reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_CSMODE, CSMODE_OFF);
// go back into flash read mode
reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_FLASH_EN, 1);
}
// test that a large chunk of memory contains (0xdeadbeef - address) or 0
int test_spiflash(uint32_t start, uint32_t size, uint8_t zero)
{
uint32_t i;
for (i = start; i < (start + size); i += 4)
{
uint32_t data = reg_read32(SPIFLASH_BASE_MEM + i);
uint32_t check = 0;
if (!zero) check = 0xdeadbeef - i;
if(data != check)
{
printf("Error reading address 0x%08x from SPI flash. Got 0x%08x, expected 0x%08x.\n", i, data, check);
return 1;
}
}
return 0;
}
// this is a variant of test_spiflash that only tests a small array of values
int check_write(uint8_t *check, uint32_t len, uint32_t addr)
{
uint32_t i;
for (i = 0; i < len; i += 4)
{
uint32_t data = reg_read32(SPIFLASH_BASE_MEM + addr + i);
uint32_t check32 = ((uint32_t *)check)[i/4];
if(check32 != data)
{
printf("Error reading address 0x%08x from SPI flash. Got 0x%02x, expected 0x%02x.\n", i + addr, data, check32);
return 1;
}
}
return 0;
}
#endif /* __SPIFLASH_H__ */

11
tests/spiflash.py Executable file
View File

@@ -0,0 +1,11 @@
#!/usr/bin/env python3
# Generates a binary file that the SPI test uses
outfile = "spiflash.img"
with open(outfile, 'wb') as f:
for i in range(0,0x100000,4):
check = 0xdeadbeef - i
f.write(check.to_bytes(4,'little'))

77
tests/spiflashread.c Normal file
View File

@@ -0,0 +1,77 @@
#include <stdlib.h>
#include <stdio.h>
#include "mmio.h"
#include "spiflash.h"
int main(void)
{
spiflash_ffmt ffmt;
ffmt.fields.cmd_en = 1;
ffmt.fields.addr_len = 4; // Valid options are 3 or 4 for our model
ffmt.fields.pad_cnt = 0; // Our SPI flash model assumes 8 dummy cycles for fast reads, 0 for slow
ffmt.fields.cmd_proto = SPIFLASH_PROTO_SINGLE; // Our SPI flash model only supports single-bit commands
ffmt.fields.addr_proto = SPIFLASH_PROTO_SINGLE; // We support both single and quad
ffmt.fields.data_proto = SPIFLASH_PROTO_SINGLE; // We support both single and quad
ffmt.fields.cmd_code = 0x13; // Slow read 4 byte
ffmt.fields.pad_code = 0x00; // Not used by our model
printf("Testing SPI flash command 0x13...\n");
configure_spiflash(ffmt);
if (test_spiflash(0x0, 0x100, 0)) return 1;
printf("Testing SPI flash command 0x03...\n");
ffmt.fields.cmd_code = 0x03; // Slow read 3 byte address
ffmt.fields.addr_len = 3; // 3 byte address
configure_spiflash(ffmt);
if (test_spiflash(0x0, 0x100, 0)) return 1;
printf("Testing SPI flash command 0x0B...\n");
ffmt.fields.cmd_code = 0x0B; // Fast read 3 byte address
ffmt.fields.pad_cnt = 8; // Needs to be 8 for fast read
configure_spiflash(ffmt);
if (test_spiflash(0x1000, 0x100, 0)) return 1;
printf("Testing SPI flash command 0x0C...\n");
ffmt.fields.cmd_code = 0x0C; // Fast read 4 byte address
ffmt.fields.addr_len = 4; // 4 byte address
configure_spiflash(ffmt);
if (test_spiflash(0x2340, 0x100, 0)) return 1;
printf("Testing SPI flash command 0x6C...\n");
ffmt.fields.cmd_code = 0x6C; // Fast read 4 byte address, quad data
ffmt.fields.data_proto = SPIFLASH_PROTO_QUAD; // Quad data
configure_spiflash(ffmt);
if (test_spiflash(0x410c, 0x100, 0)) return 1;
printf("Testing SPI flash command 0x6B...\n");
ffmt.fields.cmd_code = 0x6B; // Fast read 3 byte address, quad data
ffmt.fields.addr_len = 3;
configure_spiflash(ffmt);
if (test_spiflash(0x5ff8, 0x100, 0)) return 1;
printf("Testing SPI flash command 0xEB...\n");
ffmt.fields.cmd_code = 0xEB; // Fast read 3 byte address, quad data, quad addr
ffmt.fields.addr_proto = SPIFLASH_PROTO_QUAD;
configure_spiflash(ffmt);
if (test_spiflash(0x7c04, 0x100, 0)) return 1;
printf("Testing SPI flash command 0xEC...\n");
ffmt.fields.cmd_code = 0xEC; // Fast read 4 byte address, quad data, quad addr
ffmt.fields.addr_len = 4;
configure_spiflash(ffmt);
if (test_spiflash(0x9000, 0x100, 0)) return 1;
printf("Testing SPI flash extended range...\n");
// The provided memory image is only 1MiB, but the model has 16MiB of addressable space
// This should return 0
if (test_spiflash(0x100000, 0x100, 1)) return 1;
// This write should do nothing, so we can just re-test the first test
printf("Testing that the SPI is not writable...\n");
write_spiflash(test_data, test_len, 0x0, 0x3E, 4, SPIFLASH_PROTO_QUAD, SPIFLASH_PROTO_QUAD);
if (test_spiflash(0x0, 0x100, 0)) return 1;
return 0;
}

55
tests/spiflashwrite.c Normal file
View File

@@ -0,0 +1,55 @@
#include <stdlib.h>
#include <stdio.h>
#include "mmio.h"
#include "spiflash.h"
int main(void)
{
spiflash_ffmt ffmt;
ffmt.fields.cmd_en = 1;
ffmt.fields.addr_len = 4; // Valid options are 3 or 4 for our model
ffmt.fields.pad_cnt = 0; // Our SPI flash model assumes 8 dummy cycles for fast reads, 0 for slow
ffmt.fields.cmd_proto = SPIFLASH_PROTO_SINGLE; // Our SPI flash model only supports single-bit commands
ffmt.fields.addr_proto = SPIFLASH_PROTO_SINGLE; // We support both single and quad
ffmt.fields.data_proto = SPIFLASH_PROTO_SINGLE; // We support both single and quad
ffmt.fields.cmd_code = 0x13; // Slow read 4 byte
ffmt.fields.pad_code = 0x00; // Not used by our model
// Test that we can read
printf("Testing SPI flash command 0x13...\n");
configure_spiflash(ffmt);
if (test_spiflash(0x0, 0x100, 0)) return 1;
// 0x02: 3 byte addr, single/single
printf("Testing SPI flash command 0x02...\n");
write_spiflash(test_data, test_len, 0x200, 0x02, 3, SPIFLASH_PROTO_SINGLE, SPIFLASH_PROTO_SINGLE);
if (check_write(test_data, test_len, 0x200)) return 1;
// 0x32: 3 byte addr, single/quad
printf("Testing SPI flash command 0x32...\n");
write_spiflash(test_data, test_len, 0x300, 0x32, 3, SPIFLASH_PROTO_SINGLE, SPIFLASH_PROTO_QUAD);
if (check_write(test_data, test_len, 0x300)) return 1;
// 0x38: 3 byte addr, quad/quad
printf("Testing SPI flash command 0x38...\n");
write_spiflash(test_data, test_len, 0x400, 0x38, 3, SPIFLASH_PROTO_QUAD, SPIFLASH_PROTO_QUAD);
if (check_write(test_data, test_len, 0x400)) return 1;
// 0x12: 4 byte addr, single/single
printf("Testing SPI flash command 0x12...\n");
write_spiflash(test_data, test_len, 0x500, 0x12, 4, SPIFLASH_PROTO_SINGLE, SPIFLASH_PROTO_SINGLE);
if (check_write(test_data, test_len, 0x500)) return 1;
// 0x34: 4 byte addr, single/quad
printf("Testing SPI flash command 0x34...\n");
write_spiflash(test_data, test_len, 0x600, 0x34, 4, SPIFLASH_PROTO_SINGLE, SPIFLASH_PROTO_QUAD);
if (check_write(test_data, test_len, 0x600)) return 1;
// 0x3E: 4 byte addr, quad/quad
printf("Testing SPI flash command 0x3E...\n");
write_spiflash(test_data, test_len, 0x700, 0x3E, 4, SPIFLASH_PROTO_QUAD, SPIFLASH_PROTO_QUAD);
if (check_write(test_data, test_len, 0x700)) return 1;
return 0;
}