diff --git a/scripts/init-vlsi.sh b/scripts/init-vlsi.sh
index bbc562d4..51184e58 100755
--- a/scripts/init-vlsi.sh
+++ b/scripts/init-vlsi.sh
@@ -10,6 +10,6 @@ git submodule update --init --recursive vlsi/hammer-synopsys-plugins
 git submodule update --init --recursive vlsi/hammer-mentor-plugins
 
 # Initialize HAMMER tech plugin
-if [[ $1 != *asap7* ]]; then
+if [[ $1 != *asap7* ]] && [[ $1 != *sky130* ]]; then
     git submodule update --init --recursive vlsi/hammer-$1-plugin
 fi
diff --git a/vlsi/Makefile b/vlsi/Makefile
index e2a91865..3aaebf3b 100644
--- a/vlsi/Makefile
+++ b/vlsi/Makefile
@@ -19,7 +19,7 @@ include $(base_dir)/variables.mk
 #########################################################################################
 sim_name           ?= vcs # needed for GenerateSimFiles, but is unused
 tech_name          ?= asap7
-tech_dir           ?= $(if $(filter $(tech_name),asap7 nangate45),\
+tech_dir           ?= $(if $(filter $(tech_name),sky130 asap7 nangate45),\
                         $(vlsi_dir)/hammer/src/hammer-vlsi/technology/$(tech_name), \
                         $(vlsi_dir)/hammer-$(tech_name)-plugin/$(tech_name))
 SMEMS_COMP         ?= $(tech_dir)/sram-compiler.json
@@ -36,8 +36,12 @@ ENV_YML            ?= $(vlsi_dir)/env.yml
 INPUT_CONFS        ?= example-tools.yml \
                       $(if $(filter $(tech_name),nangate45),\
                         example-nangate45.yml,\
-                        example-asap7.yml)
-HAMMER_EXEC        ?= ./example-vlsi
+                        $(if $(filter $(tech_name),asap7),\
+							example-asap7.yml,\
+							example-sky130.yml))
+HAMMER_EXEC        ?= $(if $(filter $(tech_name),sky130),\
+                        ./example-vlsi-sky130,\
+                        ./example-vlsi)
 VLSI_TOP           ?= $(TOP)
 VLSI_HARNESS_DUT_NAME ?= chiptop
 # If overriding, this should be relative to $(vlsi_dir)
diff --git a/vlsi/example-sky130.yml b/vlsi/example-sky130.yml
new file mode 100644
index 00000000..8f5ec642
--- /dev/null
+++ b/vlsi/example-sky130.yml
@@ -0,0 +1,194 @@
+# Technology Setup
+# Technology used is Sky130
+vlsi.core.technology: sky130
+
+vlsi.core.max_threads: 12
+
+# Technology paths
+technology.sky130:
+  # sky130_pdk: "path-to-skywater-pdk/"
+  sky130_nda: "path-to-skywater-src-nda/"
+  sky130A: "path-to-sky130A/"
+  openram_lib: "path-to-sky130_sram_macros/" 
+
+# Mentor environment variables
+mentor.extra_env_vars:
+  - PDK_HOME: "path-to-skywater-src-nda/s8/V2.0.1"
+# General Hammer Inputs
+
+# Hammer will auto-generate a CPF for simple power designs; see hammer/src/hammer-vlsi/defaults.yml for more info
+vlsi.inputs.power_spec_mode: "auto"
+vlsi.inputs.power_spec_type: "cpf"
+
+# Specify clock signals
+vlsi.inputs.clocks: [
+  {name: "clock_clock", period: "20ns", uncertainty: "0.5ns"}
+]
+
+# Generate Make include to aid in flow 
+vlsi.core.build_system: make
+
+# Power Straps
+par.power_straps_mode: generate
+par.generate_power_straps_method: by_tracks
+par.blockage_spacing: 2.0
+par.generate_power_straps_options:
+  by_tracks:
+    strap_layers:
+      - met2
+      - met3
+      - met4
+      - met5
+    pin_layers:
+      - met5
+    track_width: 6
+    track_width_met5: 2
+    track_spacing: 1
+    track_start: 10
+    power_utilization: 0.2
+    power_utilization_met5: 1
+
+# Placement Constraints
+# For ASAP7, all numbers must be 4x larger than final GDS
+vlsi.inputs.placement_constraints:
+  - path: "ChipTop"
+    type: toplevel
+    x: 0
+    y: 0
+    # width: 800
+    # height: 500
+    width: 4000
+    height: 3000
+    margins:
+      left: 0
+      right: 0
+      top: 0
+      bottom: 0
+
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0"
+    type: hardmacro
+    x: 30
+    y: 2190
+    orientation: r0
+    top_layer: "met4"
+
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_1_0"
+    type: hardmacro
+    x: 30
+    y: 1530
+    orientation: mx
+    top_layer: "met4"
+
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_2_0"
+    type: hardmacro
+    x: 30
+    y: 1030
+    orientation: mx
+    top_layer: "met4"
+
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_3_0"
+    type: hardmacro
+    x: 30 
+    y: 530
+    orientation: mx
+    top_layer: "met4"
+
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_4_0"
+    type: hardmacro
+    x: 30 
+    y: 30
+    orientation: mx
+    top_layer: "met4"
+    
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_5_0"
+    type: hardmacro
+    x: 1110 
+    y: 30
+    orientation: mx
+    top_layer: "met4"
+    
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_6_0"
+    type: hardmacro
+    x: 2150 
+    y: 30
+    orientation: mx
+    top_layer: "met4"
+    
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_7_0"
+    type: hardmacro
+    x: 2150 
+    y: 530
+    orientation: mx
+    top_layer: "met4"
+    
+
+
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/data_arrays_0/data_arrays_0_0_ext/mem_0_0"
+    type: hardmacro
+    x: 2150
+    y: 1550
+    orientation: mx
+    top_layer: "met4"
+    
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/data_arrays_0/data_arrays_0_0_ext/mem_1_0"
+    type: hardmacro
+    x: 2150
+    y: 1030
+    orientation: r0
+    top_layer: "met4"
+
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/tag_array/tag_array_ext/mem_0_0"
+    type: hardmacro
+    x: 2350
+    y: 2200
+    orientation: r0
+    top_layer: "met4"
+    
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_0"
+    type: hardmacro
+    x: 3100
+    y: 30
+    orientation: "r0"
+    top_layer: "met4"
+
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_1"
+    type: hardmacro
+    x: 3100
+    y: 530
+    orientation: "r0"
+    top_layer: "met4"
+
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_2"
+    type: hardmacro
+    x: 3100
+    y: 1030
+    orientation: "r0"
+    top_layer: "met4"
+
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_3"
+    type: hardmacro
+    x: 3100
+    y: 1530
+    orientation: "r0"
+    top_layer: "met4"
+
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_4"
+    type: hardmacro
+    x: 3100
+    y: 2190
+    orientation: "r0"
+    top_layer: "met4"
+
+# Pin placement constraints
+vlsi.inputs.pin_mode: generated
+vlsi.inputs.pin.generate_mode: semi_auto
+vlsi.inputs.pin.assignments: [
+  {pins: "*", layers: ["met2", "met4"], side: "bottom"}
+]
+
+# SRAM Compiler compiler options
+vlsi.core.sram_generator_tool: "sram_compiler"
+# You should specify a location for the SRAM generator in the tech plugin
+# vlsi.core.sram_generator_tool_path: ["hammer/src/hammer-vlsi/technology/sky130"]
+vlsi.core.sram_generator_tool_path: ["/tools/B/nayiri/test/hammer/src/hammer-vlsi/technology/sky130"]
+vlsi.core.sram_generator_tool_path_meta: "append"
diff --git a/vlsi/example-vlsi-sky130 b/vlsi/example-vlsi-sky130
new file mode 100755
index 00000000..73fba530
--- /dev/null
+++ b/vlsi/example-vlsi-sky130
@@ -0,0 +1,98 @@
+#!/usr/bin/env python3
+#
+# NOTE: the custom hooks are only used for sky130.
+
+import os
+
+import hammer_vlsi
+from hammer_vlsi import CLIDriver, HammerToolHookAction
+
+from typing import Dict, Callable, Optional, List
+
+from technology.sky130 import SKY130Tech
+
+def example_place_tap_cells(x: hammer_vlsi.HammerTool) -> bool:
+    if x.get_setting("vlsi.core.technology") == "sky130":
+        x.append('''
+# TODO
+# Place custom TCL here
+''')
+    return True
+
+def example_add_fillers(x: hammer_vlsi.HammerTool) -> bool:
+    if x.get_setting("vlsi.core.technology") == "sky130":
+        x.append('''
+# TODO
+# Place custom TCL here
+''')
+    return True
+
+def example_tool_settings(x: hammer_vlsi.HammerTool) -> bool:
+    if x.get_setting("vlsi.core.technology") == "sky130":
+        x.append('''
+# TODO
+# Place custom TCL here
+set_db route_design_bottom_routing_layer 2
+set_db route_design_top_routing_layer 5
+''')
+    return True
+
+def drc_blackbox_openram_srams(x: hammer_vlsi.HammerTool) -> bool:
+    if x.get_setting("vlsi.core.technology") == "sky130":
+        drc_box = ''
+        for name in SKY130Tech().openram_sram_names():
+            drc_box += f"\nEXCLUDE CELL {name}"
+        with open(x.drc_run_file, "a") as f:
+            f.write(drc_box)
+    return True
+
+def lvs_blackbox_openram_srams(x: hammer_vlsi.HammerTool) -> bool:
+    if x.get_setting("vlsi.core.technology") == "sky130":
+        lvs_box = ''
+        for name in SKY130Tech.openram_sram_names():
+            lvs_box += f"\nLVS BOX {name}"
+            lvs_box += f"\nLVS FILTER {name} OPEN "
+        with open(x.lvs_run_file, "a") as f:
+            f.write(lvs_box)
+    return True
+
+
+class ExampleDriver(CLIDriver):
+    def get_extra_par_hooks(self) -> List[HammerToolHookAction]:
+        extra_hooks = [
+
+            # Default set of steps can be found in the CAD tool plugin's __init__.py
+
+            # make_pre_insertion_hook will execute the custom hook before the specified step
+            # SYNTAX: make_pre_insertion_hook("EXISTING_STEP", INSERTED_HOOK)
+            # hammer_vlsi.HammerTool.make_pre_insertion_hook("route_design", example_add_fillers),
+
+            # make_post_insertion_hook will execute the custom hook after the specified step
+            hammer_vlsi.HammerTool.make_post_insertion_hook("init_design", example_tool_settings),
+
+            # make_replacement_hook will replace the specified step with a custom hook
+            # hammer_vlsi.HammerTool.make_replacement_hook("place_tap_cells", example_place_tap_cells),
+
+            # make_removal_hook will remove the specified step from the flow
+            hammer_vlsi.HammerTool.make_removal_hook("place_bumps"),
+
+            # The target step in any of the above calls may be a default step or another one of your custom hooks
+        ]
+        return extra_hooks 
+    
+    def get_extra_drc_hooks(self) -> List[HammerToolHookAction]:
+        extra_hooks = [
+            # This is an example of a technology-supplied hook
+            hammer_vlsi.HammerTool.make_post_insertion_hook("generate_drc_run_file", drc_blackbox_openram_srams),
+        ]
+        return extra_hooks 
+
+    def get_extra_lvs_hooks(self) -> List[HammerToolHookAction]:
+        extra_hooks = [
+            # This is an example of a technology-supplied hook
+            hammer_vlsi.HammerTool.make_post_insertion_hook("generate_lvs_run_file", lvs_blackbox_openram_srams),
+        ]
+        return extra_hooks 
+
+if __name__ == '__main__':
+    ExampleDriver().main()