Merge pull request #826 from ucb-bar/tile-reset-async

Fix TileResetCtrl to be ahead of reset synchronizers.

generators/chipyard/src/main/scala/Clocks.scala

@@ -71,16 +71,16 @@ object ClockingSchemeGenerators {
 
     // Add a control register for each tile's reset
     val resetSetter = chiptop.lazySystem match {
-      case sys: BaseSubsystem with InstantiatesTiles => TLTileResetCtrl(sys)
+      case sys: BaseSubsystem with InstantiatesTiles => Some(TLTileResetCtrl(sys))
-      case _ => ClockGroupEphemeralNode()
+      case _ => None
     }
+    val resetSetterResetProvider = resetSetter.map(_.tileResetProviderNode).getOrElse(ClockGroupEphemeralNode())
 
     val aggregator = LazyModule(new ClockGroupAggregator("allClocks")).node
     (chiptop.implicitClockSinkNode
       := ClockGroup()
       := aggregator)
     (systemAsyncClockGroup
-      :*= resetSetter
       :*= ClockGroupNamePrefixer()
       :*= aggregator)
 
@@ -88,10 +88,16 @@ object ClockingSchemeGenerators {
     (aggregator
       := ClockGroupFrequencySpecifier(p(ClockFrequencyAssignersKey), p(DefaultClockFrequencyKey))
       := ClockGroupResetSynchronizer()
+      := resetSetterResetProvider
       := DividerOnlyClockGenerator()
       := referenceClockSource)
 
 
+    val asyncResetBroadcast = FixedClockBroadcast(None)
+    resetSetter.foreach(_.asyncResetSinkNode := asyncResetBroadcast)
+    val asyncResetSource = ClockSourceNode(Seq(ClockSourceParameters()))
+    asyncResetBroadcast := asyncResetSource
+
     InModuleBody {
       val clock_wire = Wire(Input(Clock()))
       val reset_wire = GenerateReset(chiptop, clock_wire)
@@ -103,6 +109,11 @@ object ClockingSchemeGenerators {
         o.reset := reset_wire
       }
 
+      asyncResetSource.out.unzip._1.map { o =>
+        o.clock := false.B.asClock // async reset broadcast network does not provide a clock
+        o.reset := reset_wire
+      }
+
       chiptop.harnessFunctions += ((th: HasHarnessSignalReferences) => {
         clock_io := th.harnessClock
         Nil })