[FireChip] Allow users to register new EndpointBinders in P
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@@ -1,3 +1,5 @@
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//See LICENSE for license details.
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package firesim.firesim
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package firesim.firesim
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import chisel3._
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import chisel3._
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@@ -18,19 +20,21 @@ import midas.models.{FASEDEndpoint, FasedAXI4Edge}
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import firesim.endpoints._
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import firesim.endpoints._
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import firesim.configs.MemModelKey
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import firesim.configs.MemModelKey
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// Creates a wrapper module that instantiates endpoints based on the scala type
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// Creates a wrapper FireSim harness module that instantiates endpoints based
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// of the Target (_not_ its IO). This avoids needing to duplicate environments
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// on the scala type of the Target (_not_ its IO). This avoids needing to
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// (essentially test harnesses) for each target type,
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// duplicate harnesses (essentially test harnesses) for each target.
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//
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//
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// You could just as well create a custom environment (essentially, test
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// You could just as well create a custom harness module that instantiates
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// harness) module that instantiates endpoints explicitly, or add methods to
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// endpoints explicitly, or add methods to
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// your target traits that instantiate the endpoint there (i.e., akin to
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// your target traits that instantiate the endpoint there (i.e., akin to
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// SimAXI4Mem). Since cake traits live in Rocket Chip it was easiest to match
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// SimAXI4Mem). Since cake traits live in Rocket Chip it was easiest to match
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// on the types rather than change trait code.
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// on the types rather than change trait code.
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// Determines the number of times to instantiate the DUT in the harness.
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// Subsumes legacy supernode support
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case object NumNodes extends Field[Int](1)
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case object NumNodes extends Field[Int](1)
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class DefaultFireSimEnvironment[T <: LazyModule](dutGen: () => T)(implicit val p: Parameters) extends RawModule {
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class DefaultFireSimHarness[T <: LazyModule](dutGen: () => T)(implicit val p: Parameters) extends RawModule {
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val clock = IO(Input(Clock()))
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val clock = IO(Input(Clock()))
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val reset = WireInit(false.B)
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val reset = WireInit(false.B)
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withClockAndReset(clock, reset) {
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withClockAndReset(clock, reset) {
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92
generators/firechip/src/main/scala/EndpointBinders.scala
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92
generators/firechip/src/main/scala/EndpointBinders.scala
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@@ -0,0 +1,92 @@
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//See LICENSE for license details.
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package firesim.firesim
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import chisel3._
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import chisel3.experimental.RawModule
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import freechips.rocketchip.config.{Field, Parameters, Config}
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import freechips.rocketchip.diplomacy.{LazyModule}
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import freechips.rocketchip.devices.debug.HasPeripheryDebugModuleImp
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import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPortModuleImp}
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import sifive.blocks.devices.uart.HasPeripheryUARTModuleImp
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import testchipip.{HasPeripherySerialModuleImp, HasPeripheryBlockDeviceModuleImp}
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import icenet.HasPeripheryIceNICModuleImpValidOnly
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import junctions.{NastiKey, NastiParameters}
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import midas.widgets.{IsEndpoint, PeekPokeEndpoint}
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import midas.models.{FASEDEndpoint, FasedAXI4Edge}
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import firesim.endpoints._
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import firesim.configs.MemModelKey
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// A sequence of partial functions that match on the type the DUT (_not_ it's
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// IO) to generate an appropriate endpoint. You can add your own endpoint by prepending
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// a custom PartialFunction to this Seq
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case object EndpointBinders extends Field[Seq[PartialFunction[Any, Seq[IsEndpoint]]]](Seq())
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// Config sugar that accepts a partial function and prepends it to EndpointBinders
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class RegisterEndpointBinder(pf: =>PartialFunction[Any, Seq[IsEndpoint]]) extends Config((site, here, up) => {
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case EndpointBinders => pf +: up(EndpointBinders, site)
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})
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// Default FireSim Endpoint binders follow
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class WithTiedOffDebug extends RegisterEndpointBinder({ case target: HasPeripheryDebugModuleImp =>
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target.debug.clockeddmi.foreach({ cdmi =>
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cdmi.dmi.req.valid := false.B
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cdmi.dmi.req.bits := DontCare
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cdmi.dmi.resp.ready := false.B
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cdmi.dmiClock := false.B.asClock
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cdmi.dmiReset := false.B
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})
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Seq()
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})
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class WithSerialEndpoint extends RegisterEndpointBinder({
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case target: HasPeripherySerialModuleImp => Seq(SerialEndpoint(target.serial)(target.p))
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})
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class WithNICEndpoint extends RegisterEndpointBinder({
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case target: HasPeripheryIceNICModuleImpValidOnly => Seq(NICEndpoint(target.net)(target.p))
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})
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class WithUARTEndpoint extends RegisterEndpointBinder({
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case target: HasPeripheryUARTModuleImp => target.uart.map(u => UARTEndpoint(u)(target.p))
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})
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class WithBlockDeviceEndpoint extends RegisterEndpointBinder({
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case target: HasPeripheryBlockDeviceModuleImp => Seq(BlockDevEndpoint(target.bdev, target.reset.toBool)(target.p))
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})
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class WithFASEDEndpoint extends RegisterEndpointBinder({
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case t: CanHaveMasterAXI4MemPortModuleImp =>
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implicit val p = t.p
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(t.mem_axi4 zip t.outer.memAXI4Node).flatMap({ case (io, node) =>
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(io zip node.in).map({ case (axi4Bundle, (_, edge)) =>
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val nastiKey = NastiParameters(axi4Bundle.r.bits.data.getWidth,
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axi4Bundle.ar.bits.addr.getWidth,
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axi4Bundle.ar.bits.id.getWidth)
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val fasedP = p.alterPartial({
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case NastiKey => nastiKey
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case FasedAXI4Edge => Some(edge)
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})
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FASEDEndpoint(axi4Bundle, t.reset.toBool, p(MemModelKey)(fasedP))(fasedP)
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})
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}).toSeq
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})
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class WithTracerVEndpoint extends RegisterEndpointBinder({
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case target: HasTraceIOImp => TracerVEndpoint(target.traceIO)(target.p)
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})
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// Shorthand to register all of the provided endpoints above
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class WithDefaultFireSimEndpoints extends Config(
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new WithTiedOffDebug ++
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new WithSerialEndpoint ++
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new WithNICEndpoint ++
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new WithUARTEndpoint ++
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new WithBlockDeviceEndpoint ++
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new WithFASEDEndpoint ++
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new WithTracerVEndpoint
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)
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@@ -107,6 +107,7 @@ class FireSimRocketChipConfig extends Config(
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new WithPerfCounters ++
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new WithPerfCounters ++
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new WithoutClockGating ++
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new WithoutClockGating ++
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new WithDefaultMemModel ++
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new WithDefaultMemModel ++
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new WithDefaultFireSimEndpoints ++
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new freechips.rocketchip.system.DefaultConfig)
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new freechips.rocketchip.system.DefaultConfig)
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class WithNDuplicatedRocketCores(n: Int) extends Config((site, here, up) => {
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class WithNDuplicatedRocketCores(n: Int) extends Config((site, here, up) => {
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@@ -149,6 +150,7 @@ class FireSimBoomConfig extends Config(
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new WithDefaultMemModel ++
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new WithDefaultMemModel ++
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new boom.common.WithLargeBooms ++
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new boom.common.WithLargeBooms ++
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new boom.common.WithNBoomCores(1) ++
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new boom.common.WithNBoomCores(1) ++
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new WithDefaultFireSimEndpoints ++
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new freechips.rocketchip.system.BaseConfig
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new freechips.rocketchip.system.BaseConfig
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)
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)
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@@ -61,7 +61,7 @@ class FireSimModuleImp[+L <: FireSimDUT](l: L) extends SubsystemModuleImp(l)
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with HasTraceIOImp
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with HasTraceIOImp
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with CanHaveMultiCycleRegfileImp
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with CanHaveMultiCycleRegfileImp
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class FireSim(implicit p: Parameters) extends DefaultFireSimEnvironment(() => new FireSimDUT)
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class FireSim(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireSimDUT)
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class FireSimNoNICDUT(implicit p: Parameters) extends Subsystem
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class FireSimNoNICDUT(implicit p: Parameters) extends Subsystem
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with HasHierarchicalBusTopology
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with HasHierarchicalBusTopology
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@@ -86,7 +86,7 @@ class FireSimNoNICModuleImp[+L <: FireSimNoNICDUT](l: L) extends SubsystemModule
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with CanHaveMultiCycleRegfileImp
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with CanHaveMultiCycleRegfileImp
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class FireSimNoNIC(implicit p: Parameters) extends DefaultFireSimEnvironment(() => new FireSimNoNICDUT)
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class FireSimNoNIC(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireSimNoNICDUT)
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class FireBoomDUT(implicit p: Parameters) extends Subsystem
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class FireBoomDUT(implicit p: Parameters) extends Subsystem
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with HasHierarchicalBusTopology
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with HasHierarchicalBusTopology
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@@ -113,7 +113,7 @@ class FireBoomModuleImp[+L <: FireBoomDUT](l: L) extends SubsystemModuleImp(l)
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with ExcludeInvalidBoomAssertions
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with ExcludeInvalidBoomAssertions
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with CanHaveMultiCycleRegfileImp
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with CanHaveMultiCycleRegfileImp
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class FireBoom(implicit p: Parameters) extends DefaultFireSimEnvironment(() => new FireBoomDUT)
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class FireBoom(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireBoomDUT)
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class FireBoomNoNICDUT(implicit p: Parameters) extends Subsystem
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class FireBoomNoNICDUT(implicit p: Parameters) extends Subsystem
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with HasHierarchicalBusTopology
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with HasHierarchicalBusTopology
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@@ -138,7 +138,7 @@ class FireBoomNoNICModuleImp[+L <: FireBoomNoNICDUT](l: L) extends SubsystemModu
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with ExcludeInvalidBoomAssertions
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with ExcludeInvalidBoomAssertions
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with CanHaveMultiCycleRegfileImp
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with CanHaveMultiCycleRegfileImp
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class FireBoomNoNIC(implicit p: Parameters) extends DefaultFireSimEnvironment(() => new FireBoomNoNICDUT)
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class FireBoomNoNIC(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireBoomNoNICDUT)
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class FireSimTraceGen(implicit p: Parameters) extends BaseSubsystem
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class FireSimTraceGen(implicit p: Parameters) extends BaseSubsystem
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with HasHierarchicalBusTopology
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with HasHierarchicalBusTopology
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@@ -151,5 +151,5 @@ class FireSimTraceGenModuleImp(outer: FireSimTraceGen) extends BaseSubsystemModu
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with HasTraceGenTilesModuleImp
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with HasTraceGenTilesModuleImp
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with CanHaveMasterAXI4MemPortModuleImp
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with CanHaveMasterAXI4MemPortModuleImp
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// Supernoded-ness comes from setting p(NumNodes) (see DefaultFiresimEnvironment) to something > 1
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// Supernoded-ness comes from setting p(NumNodes) (see DefaultFiresimHarness) to something > 1
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class FireSimSupernode(implicit p: Parameters) extends DefaultFireSimEnvironment(() => new FireSimDUT)
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class FireSimSupernode(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireSimDUT)
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