initial port attempt for macro compiler
This commit is contained in:
Donggyu Kim
410
tapeout/src/main/scala/transforms/macros/MacroCompiler.scala
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410
tapeout/src/main/scala/transforms/macros/MacroCompiler.scala
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@@ -0,0 +1,410 @@
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// See LICENSE for license details.
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package barstools.tapeout.transforms.macros
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import firrtl._
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import firrtl.ir._
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import firrtl.PrimOps
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import firrtl.Utils._
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import firrtl.annotations._
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import firrtl.CompilerUtils.getLoweringTransforms
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import scala.collection.mutable.{ArrayBuffer, HashMap}
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import java.io.{File, FileWriter}
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import Utils._
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object MacroCompilerAnnotation {
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def apply(c: String, mem: File, lib: Option[File], synflops: Boolean) = {
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Annotation(CircuitName(c), classOf[MacroCompilerTransform],
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s"${mem} %s ${synflops}".format(lib map (_.toString) getOrElse ""))
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}
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private val matcher = "([^ ]+) ([^ ]*) (true|false)".r
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def unapply(a: Annotation) = a match {
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case Annotation(CircuitName(c), t, matcher(mem, lib, synflops)) if t == classOf[MacroCompilerTransform] =>
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Some((c, Some(new File(mem)), if (lib.isEmpty) None else Some(new File(lib)), synflops.toBoolean))
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case _ => None
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}
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}
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class MacroCompilerPass(memFile: Option[File],
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libFile: Option[File]) extends firrtl.passes.Pass {
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require(memFile.isDefined)
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private val mems: Option[Seq[Macro]] = readJSON(memFile) map (_ map (x => new Macro(x)))
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private val libs: Option[Seq[Macro]] = readJSON(libFile) map (_ map (x => new Macro(x)))
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def compile(mem: Macro, lib: Macro): Option[(Module, ExtModule)] = {
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val pairedPorts = (
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(mem.ports filter (p => p.inputName.isDefined && !p.outputName.isDefined)) ++ // write
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(mem.ports filter (p => !p.inputName.isDefined && p.outputName.isDefined)) ++ // read
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(mem.ports filter (p => p.inputName.isDefined && p.outputName.isDefined)) // read writers
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) zip (
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(lib.ports filter (p => p.inputName.isDefined && !p.outputName.isDefined)) ++ // write
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(lib.ports filter (p => !p.inputName.isDefined && p.outputName.isDefined)) ++ // read
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(lib.ports filter (p => p.inputName.isDefined && p.outputName.isDefined)) // read writers
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)
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// Parallel mapping
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val pairs = ArrayBuffer[(BigInt, BigInt)]()
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var last = 0
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for (i <- 0 until mem.width.toInt) {
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if (i <= last + 1) {
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/* Palmer: Every memory is going to have to fit at least a single bit. */
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// coninue
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} else if ((i - last) % lib.width.toInt == 0) {
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/* Palmer: It's possible that we rolled over a memory's width here,
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if so generate one. */
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pairs += ((last, i-1))
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last = i
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} else {
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/* Palmer: FIXME: This is a mess, I must just be super confused. */
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for ((memPort, libPort) <- pairedPorts) {
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(memPort.maskGran, libPort.maskGran) match {
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case (_, Some(p)) if p == 1 => // continue
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case (Some(p), _) if i % p == 0 =>
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pairs += ((last, i-1))
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last = i
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case (_, None) => // continue
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case (_, Some(p)) if p == lib.width => // continue
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case _ =>
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System.err println "Bit-mask (or unmasked) target memories are suppored only"
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return None
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}
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}
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}
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}
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pairs += ((last, mem.width.toInt - 1))
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// Serial mapping
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val instType = BundleType(lib.ports flatMap (_.tpe.fields))
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val stmts = ArrayBuffer[Statement]()
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val selects = HashMap[String, Expression]()
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val outputs = HashMap[String, ArrayBuffer[(Expression, Expression)]]()
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/* Palmer: If we've got a parallel memory then we've got to take the
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* address bits into account. */
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if (mem.depth > lib.depth) {
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mem.ports foreach { port =>
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val high = ceilLog2(mem.depth)
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val low = ceilLog2(lib.depth)
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val ref = WRef(port.addressName)
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val name = s"${ref.name}_sel"
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selects(ref.name) = WRef(name, UIntType(IntWidth(high-low)))
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stmts += DefNode(NoInfo, name, bits(ref, high-1, low))
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}
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}
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for ((off, i) <- (0 until mem.depth.toInt by lib.depth.toInt).zipWithIndex) {
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for (j <- pairs.indices) {
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stmts += WDefInstance(NoInfo, s"mem_${i}_${j}", lib.name, instType)
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}
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for ((memPort, libPort) <- pairedPorts) {
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val addrMatch = selects get memPort.addressName match {
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case None => one
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case Some(addr) =>
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val index = UIntLiteral(i, IntWidth(bitWidth(addr.tpe)))
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DoPrim(PrimOps.Eq, Seq(addr, index), Nil, index.tpe)
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}
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def andAddrMatch(e: Expression) = and(e, addrMatch)
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val cats = ArrayBuffer[Expression]()
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for (((low, high), j) <- pairs.zipWithIndex) {
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val inst = WRef(s"mem_${i}_${j}", instType)
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def invert(exp: Expression, polarity: Option[PortPolarity]) =
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polarity match {
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case Some(ActiveLow) | Some(NegativeEdge) => not(exp)
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case _ => exp
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}
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def connectPorts(mem: Expression,
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lib: String,
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polarity: Option[PortPolarity]): Statement =
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Connect(NoInfo, WSubField(inst, lib), invert(mem, polarity))
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// Clock port mapping
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/* Palmer: FIXME: I don't handle memories with read/write clocks yet. */
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stmts += connectPorts(WRef(memPort.clockName),
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libPort.clockName,
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libPort.clockPolarity)
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// Adress port mapping
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/* Palmer: The address port to a memory is just the low-order bits of
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* the top address. */
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stmts += connectPorts(WRef(memPort.addressName),
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libPort.addressName,
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libPort.addressPolarity)
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// Output port mapping
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(memPort.outputName, libPort.outputName) match {
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case (Some(mem), Some(lib)) =>
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/* Palmer: In order to produce the output of a memory we need to cat
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* together a bunch of narrower memories, which can only be
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* done after generating all the memories. This saves up the
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* output statements for later. */
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val name = s"${mem}_${i}_${j}"
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val exp = invert(bits(WSubField(inst, lib), high-low, 0), libPort.outputPolarity)
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stmts += DefNode(NoInfo, name, exp)
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cats += WRef(name)
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case (None, Some(lib)) =>
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/* Palmer: If the inner memory has an output port but the outer
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* one doesn't then it's safe to just leave the outer
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* port floating. */
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case (None, None) =>
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/* Palmer: If there's no output ports at all (ie, read-only
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* port on the memory) then just don't worry about it,
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* there's nothing to do. */
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case (Some(mem), None) =>
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System.err println "WARNING: Unable to match output ports on memory"
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System.err println s" outer output port: ${mem}"
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return None
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}
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// Input port mapping
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(memPort.inputName, libPort.inputName) match {
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case (Some(mem), Some(lib)) =>
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/* Palmer: The input port to a memory just needs to happen in parallel,
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* this does a part select to narrow the memory down. */
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stmts += connectPorts(bits(WRef(mem), high, low), lib, libPort.inputPolarity)
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case (None, Some(lib)) =>
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/* Palmer: If the inner memory has an input port but the other
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* one doesn't then it's safe to just leave the inner
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* port floating. This should be handled by the
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* default value of the write enable, so nothing should
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* every make it into the memory. */
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case (None, None) =>
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/* Palmer: If there's no input ports at all (ie, read-only
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* port on the memory) then just don't worry about it,
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* there's nothing to do. */
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case (Some(mem), None) =>
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System.err println "WARNING: Unable to match input ports on memory"
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System.err println s" outer input port: ${mem}"
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return None
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}
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// Mask port mapping
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val memMask = memPort.maskName match {
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case Some(mem) =>
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/* Palmer: The bits from the outer memory's write mask that will be
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* used as the write mask for this inner memory. */
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if (libPort.effectiveMaskGran == libPort.width) {
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bits(WRef(mem), low / memPort.effectiveMaskGran)
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} else {
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if (libPort.effectiveMaskGran != 1) {
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// TODO
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System.err println "only single-bit mask supported"
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return None
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}
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cat(((low to high) map (i => bits(WRef(mem), i / memPort.effectiveMaskGran))).reverse)
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}
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case None =>
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/* Palmer: If there is no input port on the source memory port
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* then we don't ever want to turn on this write
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* enable. Otherwise, we just _always_ turn on the
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* write enable port on the inner memory. */
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if (!libPort.maskName.isDefined) one
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else {
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val width = libPort.width / libPort.effectiveMaskGran
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val value = (BigInt(1) << width.toInt) - 1
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UIntLiteral(value, IntWidth(width))
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}
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}
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// Write enable port mapping
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val memWriteEnable = memPort.writeEnableName match {
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case Some(mem) =>
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/* Palmer: The outer memory's write enable port, or a constant 1 if
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* there isn't a write enable port. */
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WRef(mem)
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case None =>
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/* Palemr: If there is no input port on the source memory port
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* then we don't ever want to turn on this write
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* enable. Otherwise, we just _always_ turn on the
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* write enable port on the inner memory. */
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if (!memPort.inputName.isDefined) zero else one
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}
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// Chip enable port mapping
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val memChipEnable = memPort.chipEnableName match {
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case Some(mem) => WRef(mem)
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case None => one
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}
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// Read enable port mapping
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/* Palmer: It's safe to ignore read enables, but we pass them through
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* to the vendor memory if there's a port on there that
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* implements the read enables. */
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(memPort.readEnableName, libPort.readEnableName) match {
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case (_, None) =>
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case (Some(mem), Some(lib)) =>
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stmts += connectPorts(andAddrMatch(WRef(mem)), lib, libPort.readEnablePolarity)
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case (None, Some(lib)) =>
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stmts += connectPorts(andAddrMatch(not(memWriteEnable)), lib, libPort.readEnablePolarity)
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}
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/* Palmer: This is actually the memory compiler: it figures out how to
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* implement the outer memory's collection of ports using what
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* the inner memory has availiable. */
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((libPort.maskName, libPort.writeEnableName, libPort.chipEnableName): @unchecked) match {
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case (Some(mask), Some(we), Some(en)) =>
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/* Palmer: This is the simple option: every port exists. */
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stmts += connectPorts(memMask, mask, libPort.maskPolarity)
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stmts += connectPorts(andAddrMatch(memWriteEnable), we, libPort.writeEnablePolarity)
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stmts += connectPorts(andAddrMatch(memChipEnable), en, libPort.chipEnablePolarity)
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case (Some(mask), Some(we), None) =>
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/* Palmer: If we don't have a chip enable but do have */
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stmts += connectPorts(memMask, mask, libPort.maskPolarity)
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stmts += connectPorts(andAddrMatch(and(memWriteEnable, memChipEnable)),
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we, libPort.writeEnablePolarity)
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case (None, Some(we), Some(en)) if bitWidth(memMask.tpe) == 1 =>
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/* Palmer: If we're expected to provide mask ports without a
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* memory that actually has them then we can use the
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* write enable port instead of the mask port. */
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stmts += connectPorts(andAddrMatch(and(memWriteEnable, memMask)),
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we, libPort.writeEnablePolarity)
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stmts += connectPorts(andAddrMatch(memChipEnable), en, libPort.chipEnablePolarity)
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case (None, Some(we), Some(en)) =>
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// TODO
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System.err println "cannot emulate multi-bit mask ports with write enable"
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return None
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case (None, None, None) =>
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/* Palmer: There's nothing to do here since there aren't any
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* ports to match up. */
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}
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}
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// Cat macro outputs for selection
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memPort.outputName match {
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case Some(mem) if cats.nonEmpty =>
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val name = s"${mem}_${i}"
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stmts += DefNode(NoInfo, name, cat(cats.toSeq.reverse))
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(outputs getOrElseUpdate (mem, ArrayBuffer[(Expression, Expression)]())) +=
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(addrMatch -> WRef(name))
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case _ =>
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}
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}
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}
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// Connect mem outputs
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mem.ports foreach { port =>
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port.outputName match {
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case Some(mem) => outputs get mem match {
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case Some(select) =>
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val output = (select foldRight (zero: Expression)) {
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case ((cond, tval), fval) => Mux(cond, tval, fval, fval.tpe) }
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stmts += Connect(NoInfo, WRef(mem), output)
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case None =>
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}
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case None =>
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}
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}
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Some((mem.module(Block(stmts.toSeq)), lib.blackbox))
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}
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def run(c: Circuit): Circuit = {
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val modules = (mems, libs) match {
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case (Some(mems), Some(libs)) => (mems foldLeft c.modules){ (modules, mem) =>
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val (best, cost) = (libs foldLeft (None: Option[(Module, ExtModule)], BigInt(Long.MaxValue))){
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case ((best, area), lib) if mem.ports.size != lib.ports.size =>
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/* Palmer: FIXME: This just assumes the Chisel and vendor ports are in the same
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* order, but I'm starting with what actually gets generated. */
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System.err println s"INFO: unable to compile ${mem.name} using ${lib.name} port count must match"
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(best, area)
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case ((best, area), lib) =>
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/* Palmer: A quick cost function (that must be kept in sync with
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* memory_cost()) that attempts to avoid compiling unncessary
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* memories. This is a lower bound on the cost of compiling a
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* memory: it assumes 100% bit-cell utilization when mapping. */
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// val cost = 100 * (mem.depth * mem.width) / (lib.depth * lib.width) +
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// (mem.depth * mem.width)
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// Donggyu: I re-define cost
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val cost = max(1, mem.depth / lib.depth) *
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max(1, mem.width / lib.width) *
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(lib.depth * lib.width + 1) // weights on # cells
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System.err println s"Cost of ${lib.name} for ${mem.name}: ${cost}"
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if (cost > area) (best, area)
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else compile(mem, lib) match {
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case None => (best, area)
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case Some(p) => (Some(p), cost)
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}
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}
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best match {
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case None => modules
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case Some((mod, bb)) =>
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(modules filterNot (m => m.name == mod.name || m.name == bb.name)) ++ Seq(mod, bb)
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}
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}
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case _ => c.modules
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}
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val circuit = c.copy(modules = modules)
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// print(circuit.serialize)
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circuit
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}
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}
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class MacroCompilerTransform extends Transform {
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def inputForm = HighForm
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def outputForm = HighForm
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def execute(state: CircuitState) = getMyAnnotations(state) match {
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case Seq(MacroCompilerAnnotation(state.circuit.main, mem, lib, synflops)) =>
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val transforms = Seq(
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new MacroCompilerPass(mem, lib),
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// TODO: Syn flops
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firrtl.passes.SplitExpressions
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)
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((transforms foldLeft state)((s, xform) => xform runTransform s))
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}
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}
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class MacroCompiler extends Compiler {
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def emitter = new VerilogEmitter
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def transforms =
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Seq(new MacroCompilerTransform) ++
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getLoweringTransforms(firrtl.HighForm, firrtl.LowForm) // ++
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// Seq(new LowFirrtlOptimization) // Todo: This is dangerous...
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}
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object MacroCompiler extends App {
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sealed trait MacroParam
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case object Macros extends MacroParam
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case object Library extends MacroParam
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case object Verilog extends MacroParam
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type MacroParamMap = Map[MacroParam, File]
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val usage = Seq(
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"Options:",
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" -m, --macro-list: The set of macros to compile",
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" -l, --library: The set of macros that have blackbox instances",
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" -v, --verilog: Verilog output",
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" --syn-flop: Produces synthesizable flop-based memories") mkString "\n"
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def parseArgs(map: MacroParamMap, synflops: Boolean, args: List[String]): (MacroParamMap, Boolean) =
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args match {
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case Nil => (map, synflops)
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case ("-m" | "--macro-list") :: value :: tail =>
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parseArgs(map + (Macros -> new File(value)), synflops, tail)
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case ("-l" | "--library") :: value :: tail =>
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parseArgs(map + (Library -> new File(value)), synflops, tail)
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case ("-v" | "--verilog") :: value :: tail =>
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parseArgs(map + (Verilog -> new File(value)), synflops, tail)
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case "--syn-flops" :: tail =>
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parseArgs(map, true, tail)
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case arg :: tail =>
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println(s"Unknown field $arg\n")
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throw new Exception(usage)
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}
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def run(args: List[String]) = {
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val (params, synflops) = parseArgs(Map[MacroParam, File](), false, args)
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try {
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val macros = readJSON(params get Macros).get map (x => (new Macro(x)).blackbox)
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val circuit = Circuit(NoInfo, macros, macros.last.name)
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val annotations = AnnotationMap(Seq(MacroCompilerAnnotation(
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circuit.main, params(Macros), params get Library, synflops)))
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val state = CircuitState(circuit, HighForm, Some(annotations))
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val verilog = new FileWriter(params(Verilog))
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val result = new MacroCompiler compile (state, verilog)
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verilog.close
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result
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} catch {
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case e: java.util.NoSuchElementException =>
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throw new Exception(usage)
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case e: Throwable =>
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throw e
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||||
}
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||||
}
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||||
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run(args.toList)
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}
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132
tapeout/src/main/scala/transforms/macros/Utils.scala
Normal file
132
tapeout/src/main/scala/transforms/macros/Utils.scala
Normal file
@@ -0,0 +1,132 @@
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// See LICENSE for license details.
|
||||
|
||||
package barstools.tapeout.transforms.macros
|
||||
|
||||
import firrtl._
|
||||
import firrtl.ir._
|
||||
import firrtl.PrimOps
|
||||
import firrtl.Utils.{ceilLog2, BoolType}
|
||||
import scala.util.parsing.json.JSON // Todo: this will be gone
|
||||
import java.io.File
|
||||
import scala.language.implicitConversions
|
||||
|
||||
trait PortPolarity
|
||||
case object ActiveLow extends PortPolarity
|
||||
case object ActiveHigh extends PortPolarity
|
||||
case object NegativeEdge extends PortPolarity
|
||||
case object PositiveEdge extends PortPolarity
|
||||
object PortPolarity {
|
||||
implicit def toPortPolarity(s: Any): PortPolarity =
|
||||
(s: @unchecked) match {
|
||||
case "active low" => ActiveLow
|
||||
case "active high" => ActiveHigh
|
||||
case "negative edge" => NegativeEdge
|
||||
case "positive edge" => PositiveEdge
|
||||
}
|
||||
implicit def toPortPolarity(s: Option[Any]): Option[PortPolarity] =
|
||||
s map toPortPolarity
|
||||
}
|
||||
|
||||
case class MacroPort(
|
||||
clockName: String,
|
||||
clockPolarity: Option[PortPolarity],
|
||||
addressName: String,
|
||||
addressPolarity: Option[PortPolarity],
|
||||
inputName: Option[String],
|
||||
inputPolarity: Option[PortPolarity],
|
||||
outputName: Option[String],
|
||||
outputPolarity: Option[PortPolarity],
|
||||
chipEnableName: Option[String],
|
||||
chipEnablePolarity: Option[PortPolarity],
|
||||
readEnableName: Option[String],
|
||||
readEnablePolarity: Option[PortPolarity],
|
||||
writeEnableName: Option[String],
|
||||
writeEnablePolarity: Option[PortPolarity],
|
||||
maskName: Option[String],
|
||||
maskPolarity: Option[PortPolarity],
|
||||
maskGran: Option[BigInt],
|
||||
width: BigInt,
|
||||
depth: BigInt) {
|
||||
val effectiveMaskGran = maskGran.getOrElse(width)
|
||||
private val AddrType = UIntType(IntWidth(ceilLog2(depth) max 1))
|
||||
private val DataType = UIntType(IntWidth(width))
|
||||
private val MaskType = UIntType(IntWidth(width / effectiveMaskGran))
|
||||
val tpe = BundleType(Seq(
|
||||
Field(clockName, Flip, ClockType),
|
||||
Field(addressName, Flip, AddrType)) ++
|
||||
(inputName map (Field(_, Flip, DataType))) ++
|
||||
(outputName map (Field(_, Default, DataType))) ++
|
||||
(chipEnableName map (Field(_, Flip, BoolType))) ++
|
||||
(readEnableName map (Field(_, Flip, BoolType))) ++
|
||||
(writeEnableName map (Field(_, Flip, BoolType))) ++
|
||||
(maskName map (Field(_, Flip, MaskType)))
|
||||
)
|
||||
val ports = tpe.fields map (f => Port(
|
||||
NoInfo, f.name, f.flip match { case Default => Output case Flip => Input }, f.tpe))
|
||||
}
|
||||
|
||||
class Macro(lib: Map[String, Any]) {
|
||||
val name = lib("name").asInstanceOf[String]
|
||||
val width = BigInt(lib("width").asInstanceOf[Double].toInt)
|
||||
val depth = BigInt(lib("depth").asInstanceOf[Double].toInt)
|
||||
val ports = lib("ports").asInstanceOf[List[_]] map { x =>
|
||||
val map = x.asInstanceOf[Map[String, Any]]
|
||||
MacroPort(
|
||||
map("clock port name").asInstanceOf[String],
|
||||
map get "clock port polarity",
|
||||
map("address port name").asInstanceOf[String],
|
||||
map get "address port polarity",
|
||||
map get "input port name" map (_.asInstanceOf[String]),
|
||||
map get "input port polarity",
|
||||
map get "output port name" map (_.asInstanceOf[String]),
|
||||
map get "output port polarity",
|
||||
map get "chip enable port name" map (_.asInstanceOf[String]),
|
||||
map get "chip enable port polarity",
|
||||
map get "read enable port name" map (_.asInstanceOf[String]),
|
||||
map get "read enable port polarity",
|
||||
map get "write enable port name" map (_.asInstanceOf[String]),
|
||||
map get "write enable port polarity",
|
||||
map get "mask port name" map (_.asInstanceOf[String]),
|
||||
map get "mask port polarity",
|
||||
map get "mask granularity" map (x => BigInt(x.asInstanceOf[Double].toInt)),
|
||||
width,
|
||||
depth
|
||||
)
|
||||
}
|
||||
private val modPorts = ports flatMap (_.ports)
|
||||
val blackbox = ExtModule(NoInfo, name, modPorts, name, Nil)
|
||||
def module(body: Statement) = Module(NoInfo, name, modPorts, body)
|
||||
|
||||
}
|
||||
|
||||
object Utils {
|
||||
def readJSON(file: Option[File]): Option[Seq[Map[String, Any]]] = file match {
|
||||
case None => None
|
||||
case Some(f) => try {
|
||||
(JSON parseFull io.Source.fromFile(f).mkString) match {
|
||||
case Some(p: List[Any]) => Some(
|
||||
(p foldLeft Seq[Map[String, Any]]()){
|
||||
case (res, x: Map[_, _]) =>
|
||||
val map = x.asInstanceOf[Map[String, Any]]
|
||||
if (map("type").asInstanceOf[String] == "sram") res :+ map else res
|
||||
case (res, _) => res
|
||||
}
|
||||
)
|
||||
case _ => None
|
||||
}
|
||||
} catch {
|
||||
case _: Throwable => None
|
||||
}
|
||||
}
|
||||
|
||||
def and(e1: Expression, e2: Expression) =
|
||||
DoPrim(PrimOps.And, Seq(e1, e2), Nil, e1.tpe)
|
||||
def bits(e: Expression, high: BigInt, low: BigInt): Expression =
|
||||
DoPrim(PrimOps.Bits, Seq(e), Seq(high, low), UIntType(IntWidth(high-low+1)))
|
||||
def bits(e: Expression, idx: BigInt): Expression = bits(e, idx, idx)
|
||||
def cat(es: Seq[Expression]): Expression =
|
||||
if (es.size == 1) es.head
|
||||
else DoPrim(PrimOps.Cat, Seq(es.head, cat(es.tail)), Nil, UnknownType)
|
||||
def not(e: Expression) =
|
||||
DoPrim(PrimOps.Not, Seq(e), Nil, e.tpe)
|
||||
}
|
||||
Reference in New Issue
Block a user