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WIP: Add the ability to generate a hammer-sim config for gate-level sims

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Still need to work on the asm-test/benchmark integration
This commit is contained in:
Colin Schmidt
2020-02-27 16:34:39 -08:00
parent 499f23997d
commit f3d1bb8219
3 changed files with 149 additions and 5 deletions
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114
vlsi/Makefile
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@@ -87,11 +87,123 @@ $(SRAM_CONF): $(SRAM_GENERATOR_CONF)
cd $(vlsi_dir) && $(HAMMER_EXEC) -e $(ENV_YML) $(foreach x,$(INPUT_CONFS) $(SRAM_GENERATOR_CONF), -p $(x)) --obj_dir $(build_dir) sram_generator
cd $(vlsi_dir) && cp output.json $@
#########################################################################################
# simulation input configuration
#########################################################################################
include $(base_dir)/vcs.mk
SIM_CONF = $(OBJ_DIR)/sim-inputs.yml
SIM_DEBUG_CONF = $(OBJ_DIR)/sim-debug-inputs.yml
$(SIM_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files)
mkdir -p $(dir $@)
echo "sim.inputs:" > $@
echo " level: 'gl'" >> $@
echo " input_files:" >> $@
for x in $(HARNESS_FILE) $(HARNESS_SMEMS_FILE); do \
echo ' - "'$$x'"' >> $@; \
done
echo " input_files_meta: 'append'" >> $@
echo " timescale: '1ns/10ps'" >> $@
echo " options: [" >> $@
echo " '$(RISCV)/lib/libfesvr.a'," >> $@
echo " '+lint=all,noVCDE,noONGS,noUI'," >> $@
echo " '-error=PCWM-L'," >> $@
echo " '-quiet'," >> $@
echo " '-q'," >> $@
echo " '+rad'," >> $@
echo " '+v2k'," >> $@
echo " '+vcs+lic+wait'," >> $@
echo " '+vc+list'," >> $@
echo " '-f $(sim_common_files)'," >> $@
echo " '-sverilog']" >> $@
echo " options_meta: 'append'" >> $@
echo " defines: [" >> $@
echo " 'CLOCK_PERIOD=1.0'," >> $@
echo " 'PRINTF_COND=$(TB).printf_cond'," >> $@
echo " 'STOP_COND=!$(TB).reset'," >> $@
echo " 'RANDOMIZE_MEM_INIT'," >> $@
echo " 'RANDOMIZE_REG_INIT'," >> $@
echo " 'RANDOMIZE_GARBAGE_ASSIGN'," >> $@
echo " 'RANDOMIZE_INVALID_ASSIGN']" >> $@
echo " defines_meta: 'append'" >> $@
echo " compiler_opts: [" >> $@
echo " '-I$(RISCV)/include'," >> $@
echo " '-std=c++11']" >> $@
echo " compiler_opts_meta: 'append'" >> $@
echo " execution_flags_prepend: ['$(PERMISSIVE_ON)']" >> $@
echo " execution_flags_append: ['$(PERMISSIVE_OFF)']" >> $@
echo " execution_flags: [" >> $@
echo " '+max-cycles=$(timeout_cycles)'," >> $@
for x in $(SIM_FLAGS) $(VERBOSE_FLAGS); do \
echo ' "'$$x'",' >> $@; \
done
echo " ]" >> $@
echo " execution_flags_meta: 'append'" >> $@
echo " benchmarks: ['$(RISCV)/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-dgemm-opt.riscv']" >> $@
$(SIM_DEBUG_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files)
mkdir -p $(dir $@)
echo "sim.inputs:" > $@
echo " level: 'gl'" >> $@
echo " input_files:" >> $@
for x in $(HARNESS_FILE) $(HARNESS_SMEMS_FILE); do \
echo ' - "'$$x'"' >> $@; \
done
echo " input_files_meta: 'append'" >> $@
echo " timescale: '1ns/10ps'" >> $@
echo " options: [" >> $@
echo " '$(RISCV)/lib/libfesvr.a'," >> $@
echo " '+lint=all,noVCDE,noONGS,noUI'," >> $@
echo " '-error=PCWM-L'," >> $@
echo " '-quiet'," >> $@
echo " '-q'," >> $@
echo " '+rad'," >> $@
echo " '+v2k'," >> $@
echo " '+vcs+lic+wait'," >> $@
echo " '+vc+list'," >> $@
echo " '-f $(sim_common_files)'," >> $@
echo " '-sverilog'," >> $@
echo " '-debug_pp']" >> $@
echo " options_meta: 'append'" >> $@
echo " defines: [" >> $@
echo " 'DEBUG'," >> $@
echo " 'CLOCK_PERIOD=1.0'," >> $@
echo " 'PRINTF_COND=$(TB).printf_cond'," >> $@
echo " 'STOP_COND=!$(TB).reset'," >> $@
echo " 'RANDOMIZE_MEM_INIT'," >> $@
echo " 'RANDOMIZE_REG_INIT'," >> $@
echo " 'RANDOMIZE_GARBAGE_ASSIGN'," >> $@
echo " 'RANDOMIZE_INVALID_ASSIGN']" >> $@
echo " defines_meta: 'append'" >> $@
echo " compiler_opts: [" >> $@
echo " '-I$(RISCV)/include'," >> $@
echo " '-std=c++11']" >> $@
echo " compiler_opts_meta: 'append'" >> $@
echo " execution_flags_prepend: ['$(PERMISSIVE_ON)']" >> $@
echo " execution_flags_append: ['$(PERMISSIVE_OFF)']" >> $@
echo " execution_flags: [" >> $@
echo " '+max-cycles=$(timeout_cycles)'," >> $@
for x in $(SIM_FLAGS) $(VERBOSE_FLAGS); do \
echo ' "'$$x'",' >> $@; \
done
echo " '+vcdplusfile=$(OBJ_DIR)/sim-tool-output.vpd']" >> $@
echo " execution_flags_meta: 'append'" >> $@
echo " tb_dut: 'testHarness.top'" >> $@
echo " benchmarks: ['$(RISCV)/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-dgemm-opt.riscv']" >> $@
#echo " benchmarks: ['$(RISCV)/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-add']" >> $@
$(POWER_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files)
mkdir -p $(dir $@)
echo "power.inputs:" > $@
sim_conf_temp: $(SIM_CONF) $(SIM_DEBUG_CONF)
#########################################################################################
# synthesis input configuration
#########################################################################################
SYN_CONF = $(OBJ_DIR)/inputs.yml
GENERATED_CONFS = $(SYN_CONF)
GENERATED_CONFS = $(SYN_CONF) $(SIM_CONF)
ifeq ($(CUSTOM_VLOG), )
GENERATED_CONFS += $(if $(filter $(tech_name), asap7), , $(SRAM_CONF))
endif