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Remove references to old ringsbus

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This commit is contained in:
Jerry Zhao
2023-02-11 12:54:50 -08:00
parent 0190da20f0
commit f321d7bd3b
2 changed files with 5 additions and 9 deletions
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12
docs/Customization/Memory-Hierarchy.rst
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@@ -42,15 +42,9 @@ The System Bus
-------------- --------------
The system bus is the TileLink network that sits between the tiles and the L2 The system bus is the TileLink network that sits between the tiles and the L2
agents and MMIO peripherals. Ordinarily, it is a fully-connected crossbar, agents and MMIO peripherals. Ordinarily, it is a fully-connected crossbar, but
but TestChipIP provides a version that uses a ring network instead. This can a network-on-chip-based implementation can be generated using Constellation.
be useful when taping out larger systems. To use the ring network system See :ref:`Customization/NoC-SoCs:SoCs with NoC-based Interconnects` for more.
bus, simply add the ``WithRingSystemBus`` config fragment to your configuration.
.. literalinclude:: ../../generators/chipyard/src/main/scala/config/RocketConfigs.scala
:language: scala
:start-after: DOC include start: RingSystemBusRocket
:end-before: DOC include end: RingSystemBusRocket
The SiFive L2 Cache The SiFive L2 Cache
------------------- -------------------

2
docs/Customization/NoC-SoCs.rst
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@@ -1,3 +1,5 @@
.. _noc-socs:
SoCs with NoC-based Interconnects SoCs with NoC-based Interconnects
================================== ==================================