Add Pads + other utilities (#7)
[stevo]: adds a bunch of pad frame commits, as well as beginning work on clocking annotations and constraints * start add io pads pass * save progress adding yaml pad info * saving some semi-presentable work -- parses yaml for pad templates and associates templates with ports * added black boxes to the module; still need to hook up * added supply pad yaml example; added option to not include pad for an IO, blackboxed that cat + bit extraction functions * rewrite createbbs and some other parts of the transform * finally got blackboxhelper to work -- seems there was a typo in the firrtl pass (?) have not connected them up properly in the padframe * finished first version of pad transform; need to add bells and whistles + special case stuff * made a bunch of changes in firrtl to shorthand things * done with padframe for signals * started major refactoring; first of pad yaml stuff * forgot to update verilogTemplate -> verilog * rename ParsePadYaml -> ChipPadsYaml; moved some stuff * separated out stuff that describes pads i.e. direction, type, side * forgot to update import for yamlhelpers * trying to make the process of creating annotations more structured * saving annotation helpers but prob better to switch to yaml * saving changes -- reworking annotations * fixing some bugs; properly annotated ports with pads * annotate supply pads * lesson (re)learned. cleaned up constants * finished adding supply pads to pad frame; still need to generate io file * also committing updated transform; still without io file * big typo was causing pad verilog files not to be generated * verilator passes with transform; had to fix verilog bb typo * added unused pads; added more thorough tests + did visual inspection of output; made some port types more explicit * renamed files/classes to be clearer * started creating pad io template * update spec so that transform order matters * get rid of logger * went around in circles with blackboxhelper + way to annotate * finished adding + testing pad.io creation * starting clkgen pass -- made model for asynchronously reset clk divider + wrappers for programmatic bundling * temporarily locating albert's utility functions here * saving work on clk constraints * redid input config passing -- pass in tech directory instead; seems like getting clk sink, src, and relationship works * not done; need to pause to do tapeout-y things. the clk gen pass gets all the clks and their sources, but i need to build a proper graph to handle clks coming out of muxes
This commit is contained in:
Angie Wang
181
tapeout/src/test/scala/transforms/clkgen/ClkGenSpec.scala
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181
tapeout/src/test/scala/transforms/clkgen/ClkGenSpec.scala
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@@ -0,0 +1,181 @@
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// See LICENSE for license details.
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package barstools.tapeout.transforms.clkgen
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import chisel3._
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import firrtl._
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import org.scalatest.{FlatSpec, Matchers}
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import chisel3.experimental._
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import chisel3.iotesters._
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import chisel3.util.HasBlackBoxInline
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import barstools.tapeout.transforms.pads.TopModule
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// Purely to see that clk src tagging works with BBs
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class FakeBBClk extends BlackBox with HasBlackBoxInline with IsClkModule {
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val io = IO(new Bundle {
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val inClk = Input(Clock())
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val outClk = Output(Vec(3, Clock()))
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})
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annotateClkPort(io.inClk, Sink())
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val generatedClks = io.outClk.map { case elt =>
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val id = getIOName(elt)
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val srcId = getIOName(io.inClk)
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annotateClkPort(elt.asInstanceOf[Element])
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GeneratedClk(id, Seq(srcId), Seq(0, 1, 2))
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}.toSeq
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annotateDerivedClks(ClkDiv, generatedClks)
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// Generates a "FakeBB.v" file with the following Verilog module
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setInline("FakeBBClk.v",
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s"""
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|module FakeBBClk(
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| input inClk,
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| output outClk_0,
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| output outClk_1,
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| output outClk_2
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|);
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| always @* begin
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| outClk_0 = inClk;
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| outClk_1 = inClk;
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| outClk_2 = inClk;
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| end
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|endmodule
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""".stripMargin)
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}
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class ModWithNestedClkIO(numPhases: Int) extends Bundle {
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val inClk = Input(Clock())
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val bbOutClk = Output(Vec(3, Clock()))
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val clkDivOut = Output(Vec(numPhases, Clock()))
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}
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class TestModWithNestedClkIO(numPhases: Int) extends Bundle {
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val bbOutClk = Output(Vec(3, Bool()))
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val clkDivOut = Output(Vec(numPhases, Bool()))
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}
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class ModWithNestedClk(divBy: Int, phases: Seq[Int], syncReset: Boolean) extends Module {
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val io = IO(new ModWithNestedClkIO(phases.length))
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val bb = Module(new FakeBBClk)
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bb.io.inClk := io.inClk
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io.bbOutClk := bb.io.outClk
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val clkDiv = Module(new SEClkDivider(divBy, phases, syncReset = syncReset))
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clkDiv.io.reset := reset
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clkDiv.io.inClk := io.inClk
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phases.zipWithIndex.foreach { case (phase, idx) => io.clkDivOut(idx) := clkDiv.io.outClks(phase) }
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}
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class TopModuleWithClks(val divBy: Int, val phases: Seq[Int]) extends TopModule(usePads = false) {
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val io = IO(new Bundle {
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val gen1 = new TestModWithNestedClkIO(phases.length)
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val gen2 = new TestModWithNestedClkIO(phases.length)
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val gen3 = new TestModWithNestedClkIO(phases.length)
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val fakeClk1 = Input(Clock())
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val fakeClk2 = Input(Clock())
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})
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// TODO: Don't have to type Some
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annotateClkPort(clock,
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id = "clock", // not in io bundle
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sink = Sink(Some(ClkSrc(period = 5.0, async = Seq(getIOName(io.fakeClk1)))))
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)
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annotateClkPort(io.fakeClk1, Sink(Some(ClkSrc(period = 4.0))))
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annotateClkPort(io.fakeClk2, Sink(Some(ClkSrc(period = 3.0))))
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// Most complicated: test chain of clock generators
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val gen1 = Module(new ModWithNestedClk(divBy, phases, syncReset = true))
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io.gen1.bbOutClk := Vec(gen1.io.bbOutClk.map(x => x.asUInt))
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io.gen1.clkDivOut := Vec(gen1.io.clkDivOut.map(x => x.asUInt))
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gen1.io.inClk := clock
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// ClkDiv on generated clk -> reset occurs before first input clk edge
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val gen2 = Module(new ModWithNestedClk(divBy, phases, syncReset = false))
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io.gen2.bbOutClk := Vec(gen2.io.bbOutClk.map(x => x.asUInt))
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io.gen2.clkDivOut := Vec(gen2.io.clkDivOut.map(x => x.asUInt))
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gen2.io.inClk := gen1.io.clkDivOut.last
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val gen3 = Module(new ModWithNestedClk(divBy, phases, syncReset = false))
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io.gen3.bbOutClk := Vec(gen3.io.bbOutClk.map(x => x.asUInt))
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io.gen3.clkDivOut := Vec(gen3.io.clkDivOut.map(x => x.asUInt))
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gen3.io.inClk := gen1.io.clkDivOut.last
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}
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class TopModuleWithClksTester(c: TopModuleWithClks) extends PeekPokeTester(c) {
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val maxT = c.divBy * c.divBy * 4
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val numSubClkOutputs = c.io.gen1.clkDivOut.length
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val gen1Out = Seq.fill(numSubClkOutputs)(scala.collection.mutable.ArrayBuffer[Int]())
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val gen2Out = Seq.fill(numSubClkOutputs)(scala.collection.mutable.ArrayBuffer[Int]())
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val gen3Out = Seq.fill(numSubClkOutputs)(scala.collection.mutable.ArrayBuffer[Int]())
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reset(10)
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for (t <- 0 until maxT) {
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for (k <- 0 until numSubClkOutputs) {
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gen1Out(k) += peek(c.io.gen1.clkDivOut(k)).intValue
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gen2Out(k) += peek(c.io.gen2.clkDivOut(k)).intValue
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gen3Out(k) += peek(c.io.gen3.clkDivOut(k)).intValue
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}
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step(1)
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}
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val clkCounts = (0 until maxT)
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val clkCountsModDiv = clkCounts.map(_ % c.divBy)
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for (k <- 0 until numSubClkOutputs) {
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val expected = clkCountsModDiv.map(x => if (x == c.phases(k)) 1 else 0)
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expect(gen1Out(k) == expected, s"gen1Out($k) incorrect!")
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println(s"gen1Out($k): \t${gen1Out(k).mkString("")}")
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}
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val gen1ClkCounts = (0 until maxT/c.divBy).map(i => Seq.fill(c.divBy)(i)).flatten
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val gen1ClkCountsModDiv = gen1ClkCounts.map(_ % c.divBy)
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for (k <- 0 until numSubClkOutputs) {
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// Handle initial transient
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val fillVal = if (c.phases.last == c.divBy - 1 && k == numSubClkOutputs - 1) 1 else 0
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val expected = Seq.fill(c.phases.last)(fillVal) ++
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gen1ClkCountsModDiv.map(x => if (x == c.phases(k)) 1 else 0).dropRight(c.phases.last)
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expect(gen2Out(k) == expected, s"gen1Out($k) incorrect!")
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println(s"gen2Out($k): \t${gen2Out(k).mkString("")}")
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println(s"expected: \t${expected.mkString("")}")
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}
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expect(gen2Out == gen3Out, "gen2Out should equal gen3Out")
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}
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class ClkGenSpec extends FlatSpec with Matchers {
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def readOutputFile(dir: String, f: String): String =
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scala.io.Source.fromFile(Seq(dir, f).mkString("/")).getLines.mkString("\n")
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def readResource(resource: String): String = {
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val stream = getClass.getResourceAsStream(resource)
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scala.io.Source.fromInputStream(stream).mkString
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}
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def checkOutputs(dir: String) = {
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}
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behavior of "top module with clk gens"
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it should "pass simple testbench" in {
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val optionsManager = new TesterOptionsManager {
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firrtlOptions = firrtlOptions.copy(
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compilerName = "verilog"
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/*annotations = List(passes.clocklist.ClockListAnnotation(
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s"-c:TopModuleWithClks:-m:TopModuleWithClks:-o:test.clk"
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)),
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customTransforms = Seq(new passes.clocklist.ClockListTransform())*/
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)
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testerOptions = testerOptions.copy(isVerbose = false, backendName = "verilator", displayBase = 10)
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commonOptions = commonOptions.copy(targetDirName = "test_run_dir/ClkTB")
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}
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// WARNING: TB requires that phase divBy - 1 should be at the end of the Seq to be OK during initial transient
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iotesters.Driver.execute(() => new TopModuleWithClks(4, Seq(0, 1, 3)), optionsManager) { c =>
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val dir = optionsManager.commonOptions.targetDirName
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checkOutputs(dir)
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new TopModuleWithClksTester(c)
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} should be (true)
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}
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}
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226
tapeout/src/test/scala/transforms/pads/AddIOPadsSpec.scala
Normal file
226
tapeout/src/test/scala/transforms/pads/AddIOPadsSpec.scala
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@@ -0,0 +1,226 @@
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// See LICENSE for license details.
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package barstools.tapeout.transforms.pads
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import chisel3._
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import firrtl._
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import org.scalatest.{FlatSpec, Matchers}
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import chisel3.experimental._
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import chisel3.util.HasBlackBoxInline
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import chisel3.iotesters._
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class BB extends BlackBox with HasBlackBoxInline {
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val io = IO(new Bundle {
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val c = Input(SInt(14.W))
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val z = Output(SInt(16.W))
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val analog1 = Analog(3.W)
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val analog2 = analog1.chiselCloneType
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})
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// Generates a "FakeBB.v" file with the following Verilog module
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setInline("FakeBB.v",
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s"""
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|module BB(
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| input [15:0] c,
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| output [15:0] z,
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| inout [2:0] analog1,
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| inout [2:0] analog2
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|);
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| always @* begin
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| z = 2 * c;
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| analog2 = analog1 + 1;
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| end
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|endmodule
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""".stripMargin)
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}
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// If no template file is provided, it'll use the default one (example) in the resource folder
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// Default pad side is Top if no side is specified for a given IO
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// You can designate the number of different supply pads on each chip side
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class ExampleTopModuleWithBB extends TopModule(
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supplyAnnos = Seq(
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SupplyAnnotation(padName = "vdd", leftSide = 3, bottomSide = 2),
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SupplyAnnotation(padName = "vss", rightSide = 1)
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)) {
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val io = IO(new Bundle {
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val a = Input(UInt(15.W))
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val b = a.chiselCloneType
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val c = Input(SInt(14.W))
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val x = Output(UInt(16.W))
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val y = x.chiselCloneType
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val z = Output(SInt(16.W))
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val analog1 = Analog(3.W)
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val analog2 = analog1.chiselCloneType
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val v = Output(Vec(3, UInt(5.W)))
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})
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// Can annotate aggregates with pad side location + pad name (should be a name in the yaml template)
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annotatePad(io.v, Right, "from_tristate_foundry")
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// Can annotate individual elements
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annotatePad(io.analog1, Left, "fast_custom")
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annotatePad(io.analog2, Bottom, "slow_foundry")
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// Looks for a pad that matches the IO type (digital in, digital out, analog) if no name is specified
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Seq(io.a, io.b, io.c, io.x) foreach { x => annotatePad(x, Left) }
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// Some signals might not want pads associated with them
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noPad(io.y)
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// Clk might come directly from bump
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noPad(clock)
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val bb = Module(new BB())
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bb.io.c := io.c
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io.z := bb.io.z
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bb.io.analog1 <> io.analog1
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bb.io.analog2 <> io.analog2
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io.x := io.a + 1.U
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io.y := io.b - 1.U
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io.v foreach { lhs => lhs := io.a }
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}
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class SimpleTopModuleTester(c: ExampleTopModuleWithBB) extends PeekPokeTester(c) {
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val ax = Seq(5, 3)
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val bx = Seq(8, 2)
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val cx = Seq(-11, -9)
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for (i <- 0 until ax.length) {
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poke(c.io.a, ax(i))
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poke(c.io.b, bx(i))
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poke(c.io.c, cx(i))
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expect(c.io.x, ax(i) + 1)
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expect(c.io.y, bx(i) - 1)
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expect(c.io.z, 2 * cx(i))
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c.io.v foreach { out => expect(out, ax(i)) }
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}
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// Analog can't be peeked + poked
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}
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// Notes: Annotations
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// a in 15: left, default digital
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// b in 15: left, default digital
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// c in 14: left, default digital ; signed
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// x out 16: left, default digital
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// y out: NOPAD
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// clk in: NOPAD
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// analog1 3: left, fast_custom
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// analog2 3: bottom, slow_foundry
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// v (vec of 3 with 5, out): right, from_tristate_foundry
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// reset in: UNSPECIFIED: top, default digital
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// z out 16: UNSPECIFIED: top, default digital ; signed
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// vdd, left: 3, group of 1
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// vdd, bottom: 2, group of 1
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// vss, right: 1, group of 2
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// Notes: Used pads
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// digital horizontal (from_tristate_foundry)
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// in + out
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// analog fast_custom horizontal
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// analog slow_foundry vertical
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// digital vertical (from_tristate_foundry)
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// in + out
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// vdd horizontal
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// vdd vertical
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// vss horizontal
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class IOPadSpec extends FlatSpec with Matchers {
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def readOutputFile(dir: String, f: String): String =
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scala.io.Source.fromFile(Seq(dir, f).mkString("/")).getLines.mkString("\n")
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def readResource(resource: String): String = {
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val stream = getClass.getResourceAsStream(resource)
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scala.io.Source.fromInputStream(stream).mkString
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}
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def checkOutputs(dir: String) = {
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// Show that black box source helper is run
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//readOutputFile(dir, "black_box_verilog_files.f") should include ("pad_supply_vdd_horizontal.v")
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val padBBEx = s"""// Digital Pad Example
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|// Signal Direction: Input
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|// Pad Orientation: Horizontal
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|// Call your instance PAD
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|module pad_digital_from_tristate_foundry_horizontal_input(
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| input in,
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| output reg out
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|);
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| // Where you would normally dump your pad instance
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| always @* begin
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| out = in;
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| end
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|endmodule
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|
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|module pad_digital_from_tristate_foundry_horizontal_input_array #(
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| parameter int WIDTH=1
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|)(
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| input [WIDTH-1:0] in,
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| output reg [WIDTH-1:0] out
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|);
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| pad_digital_from_tristate_foundry_horizontal_input pad_digital_from_tristate_foundry_horizontal_input[WIDTH-1:0](
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| .in(in),
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| .out(out)
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| );""".stripMargin
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// Make sure black box templating is OK
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readOutputFile(dir, "pad_digital_from_tristate_foundry_horizontal_input_array.v") should include (padBBEx)
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val verilog = readOutputFile(dir, "ExampleTopModuleWithBB.v")
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// Pad frame + top should be exact
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verilog should include (readResource("/PadAnnotationVerilogPart.v"))
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// Pad Placement IO file should be exact
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val padIO = readOutputFile(dir, "pads.io")
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padIO should include(readResource("/PadPlacement.io"))
|
||||
}
|
||||
|
||||
behavior of "top module with blackbox"
|
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|
||||
import barstools.tapeout.transforms._
|
||||
|
||||
it should "pass simple testbench" in {
|
||||
val optionsManager = new TesterOptionsManager {
|
||||
firrtlOptions = firrtlOptions.copy(
|
||||
compilerName = "verilog"
|
||||
// annotations = List(TechnologyLocation("./RealTech"))
|
||||
)
|
||||
testerOptions = testerOptions.copy(isVerbose = true, backendName = "verilator", displayBase = 10)
|
||||
commonOptions = commonOptions.copy(targetDirName = "test_run_dir/PadsTB")
|
||||
}
|
||||
iotesters.Driver.execute(() => new ExampleTopModuleWithBB, optionsManager) { c =>
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||||
val dir = optionsManager.commonOptions.targetDirName
|
||||
checkOutputs(dir)
|
||||
new SimpleTopModuleTester(c)
|
||||
} should be (true)
|
||||
}
|
||||
/*
|
||||
it should "create proper IO pads + black box in low firrtl" in {
|
||||
val optionsManager = new ExecutionOptionsManager("barstools") with HasChiselExecutionOptions with HasFirrtlOptions {
|
||||
firrtlOptions = firrtlOptions.copy(compilerName = "low")
|
||||
commonOptions = commonOptions.copy(targetDirName = "test_run_dir/LoFirrtl")
|
||||
//commonOptions = commonOptions.copy(globalLogLevel = logger.LogLevel.Info)
|
||||
}
|
||||
val success = chisel3.Driver.execute(optionsManager, () => new ExampleTopModuleWithBB) match {
|
||||
case ChiselExecutionSuccess(_, chirrtl, Some(FirrtlExecutionSuccess(_, firrtl))) =>
|
||||
firrtl should include ("ExampleTopModuleWithBB_PadFrame")
|
||||
firrtl should include ("ExampleTopModuleWithBB_Internal")
|
||||
firrtl should not include ("FakeBBPlaceholder")
|
||||
true
|
||||
case _ => false
|
||||
}
|
||||
success should be (true)
|
||||
}
|
||||
*/
|
||||
it should "create proper IO pads + black box in verilog" in {
|
||||
val optionsManager = new ExecutionOptionsManager("barstools") with HasChiselExecutionOptions with HasFirrtlOptions {
|
||||
firrtlOptions = firrtlOptions.copy(
|
||||
compilerName = "verilog"
|
||||
)
|
||||
commonOptions = commonOptions.copy(targetDirName = "test_run_dir/PadsVerilog")
|
||||
//commonOptions = commonOptions.copy(globalLogLevel = logger.LogLevel.Info)
|
||||
}
|
||||
val success = chisel3.Driver.execute(optionsManager, () => new ExampleTopModuleWithBB) match {
|
||||
case ChiselExecutionSuccess(_, chirrtl, Some(FirrtlExecutionSuccess(_, verilog))) =>
|
||||
true
|
||||
case _ => false
|
||||
}
|
||||
success should be (true)
|
||||
val dir = optionsManager.commonOptions.targetDirName
|
||||
checkOutputs(dir)
|
||||
}
|
||||
|
||||
}
|
||||
Reference in New Issue
Block a user