Add Pads + other utilities (#7)

[stevo]: adds a bunch of pad frame commits, as well as beginning work on clocking annotations and constraints


* start add io pads pass

* save progress adding yaml pad info

* saving some semi-presentable work -- parses yaml for pad templates and associates templates with ports

* added black boxes to the module; still need to hook up

* added supply pad yaml example; added option to not include pad for an IO, blackboxed that cat + bit extraction functions

* rewrite createbbs and some other parts of the transform

* finally got blackboxhelper to work -- seems there was a typo in the firrtl pass (?) have not connected them up properly in the padframe

* finished first version of pad transform; need to add bells and whistles + special case stuff

* made a bunch of changes in firrtl to shorthand things

* done with padframe for signals

* started major refactoring; first of pad yaml stuff

* forgot to update verilogTemplate -> verilog

* rename ParsePadYaml -> ChipPadsYaml; moved some stuff

* separated out stuff that describes pads i.e. direction, type, side

* forgot to update import for yamlhelpers

* trying to make the process of creating annotations more structured

* saving annotation helpers but prob better to switch to yaml

* saving changes -- reworking annotations

* fixing some bugs; properly annotated ports with pads

* annotate supply pads

* lesson (re)learned. cleaned up constants

* finished adding supply pads to pad frame; still need to generate io file

* also committing updated transform; still without io file

* big typo was causing pad verilog files not to be generated

* verilator passes with transform; had to fix verilog bb typo

* added unused pads; added more thorough tests + did visual inspection of output; made some port types more explicit

* renamed files/classes to be clearer

* started creating pad io template

* update spec so that transform order matters

* get rid of logger

* went around in circles with blackboxhelper + way to annotate

* finished adding + testing pad.io creation

* starting clkgen pass -- made model for asynchronously reset clk divider + wrappers for programmatic bundling

* temporarily locating albert's utility functions here

* saving work on clk constraints

* redid input config passing -- pass in tech directory instead; seems like getting clk sink, src, and relationship works

* not done; need to pause to do tapeout-y things. the clk gen pass gets all the clks and their sources, but i need to build a proper graph to handle clks coming out of muxes

tapeout/src/main/resources/FoundryPads.yaml

@@ -0,0 +1,113 @@
+# Pad types must be one of digital, analog, or supply; pad names must be unique!
+# This just shows you how you can template things with {{}}, if/else,  and the following parameters:
+# isInput: Boolean (each digital pad entry should be configurable between both input and output)
+# isHorizontal: Boolean (each pad entry should be configurable between both horizontal and vertical)
+# NOTE: Expects 1-bit in/out to be named in/out for digital; and 1-bit io for analog (supplies don't have ports)
+# Expects module name to be obtained from {{name}} which is derived from yaml name, tpe in the Firrtl pass
+# Pipe is used for stripping margins, but indentation is required before the pipe for the yaml reader to work
+---
+tpe: analog
+name: slow_foundry
+width: 0
+height: 0
+verilog: |
+  |// Foundry Analog Pad Example
+  |// Pad Orientation: {{#if isHorizontal}}Horizontal{{else}}Vertical{{/if}}
+  |// Call your instance PAD
+  |module {{name}}(
+  |  inout io
+  |);
+  |endmodule
+---
+tpe: analog
+name: fast_custom
+width: 0
+height: 0
+verilog: |
+  |// Custom Analog Pad Example
+  |// Pad Orientation: {{#if isHorizontal}}Horizontal{{else}}Vertical{{/if}}
+  |// Call your instance PAD
+  |module {{name}}(
+  |  inout io
+  |);
+  |endmodule
+---
+tpe: digital
+name: from_tristate_foundry
+width: 0
+height: 0
+verilog: |
+  |// Digital Pad Example
+  |// Signal Direction: {{#if isInput}}Input{{else}}Output{{/if}}
+  |// Pad Orientation: {{#if isHorizontal}}Horizontal{{else}}Vertical{{/if}}
+  |// Call your instance PAD
+  |module {{name}}(
+  |  input in,
+  |  output reg out
+  |);
+  |  // Where you would normally dump your pad instance
+  |  always @* begin
+  |    out = in;
+  |  end
+  |endmodule
+---
+tpe: digital
+name: fake_digital
+width: 0
+height: 0
+verilog: |
+  |// (Fake/Unused) Digital Pad Example
+  |// Signal Direction: {{#if isInput}}Input{{else}}Output{{/if}}
+  |// Pad Orientation: {{#if isHorizontal}}Horizontal{{else}}Vertical{{/if}}
+  |// Call your instance PAD
+  |module {{name}}(
+  |  input in,
+  |  output reg out
+  |);
+  |  // Where you would normally dump your pad instance
+  |  always @* begin
+  |    out = in;
+  |  end
+  |endmodule
+---
+tpe: supply
+name: vdd
+width: 0
+height: 0
+supplySetNum: 1
+verilog: |
+  |// VDD Pad Example (No IO)
+  |// Can group some number together as required by the foundry
+  |// Pad Orientation: {{#if isHorizontal}}Horizontal{{else}}Vertical{{/if}}
+  |// Call your instance array PAD[0:0], PAD[2:0], etc.
+  |module {{name}}(
+  |);
+  |endmodule
+---
+tpe: supply
+name: vss
+width: 0
+height: 0
+supplySetNum: 2
+verilog: |
+  |// VSS Pad Example (No IO)
+  |// Can group some number together as required by the foundry
+  |// Pad Orientation: {{#if isHorizontal}}Horizontal{{else}}Vertical{{/if}}
+  |// Call your instance array PAD[0:0], PAD[2:0], etc.
+  |module {{name}}(
+  |);
+  |endmodule
+---
+tpe: supply
+name: avss
+width: 0
+height: 0
+supplySetNum: 1
+verilog: |
+  |// Analog VSS Pad Example (No IO)
+  |// Can group some number together as required by the foundry
+  |// Pad Orientation: {{#if isHorizontal}}Horizontal{{else}}Vertical{{/if}}
+  |// Call your instance array PAD[0:0], PAD[2:0], etc.
+  |module {{name}}(
+  |);
+  |endmodule

tapeout/src/main/resources/PadPlacement.yaml

@@ -0,0 +1,43 @@
+# Example for Innovus: https://legacy.iis.ee.ethz.ch/~vlsi2/ex05/ex05.pdf
+---
+file: pads.io
+left: "1"             # Bottom to top
+top: "2"              # Left to right
+right: "3"            # Bottom to top
+bottom: "4"           # Left to right
+# Note: In your scripts, you should specify instance array styles
+# i.e. hdl_instance_array_naming_style string (For Genus)
+instanceArray: "{{signal}}[{{idx}}]"
+padLine: |
+  |    (inst name = "{{padInst}}")   # Side: {{side}}, Order: {{padIdx}}
+template: |
+  |(globals
+  |  version = 3
+  |  io_order = default
+  |)
+  |(iopad
+  |  (bottomleft
+  |    (inst name="corner_ll" cell="CORNER_EXAMPLE" )
+  |  ) 
+  |  (bottomright 
+  |    (inst name="corner_lr" orientation=MY cell="CORNER_EXAMPLE" ) 
+  |  ) 
+  |  (topleft 
+  |    (inst name="corner_ul" orientation=MX cell="CORNER_EXAMPLE" ) 
+  |  ) 
+  |  (topright 
+  |    (inst name="corner_ur" cell="CORNER_EXAMPLE" ) 
+  |  ) 
+  |  (left
+  |{{leftPads}}
+  |  )
+  |  (right
+  |{{rightPads}}
+  |  )
+  |  (top
+  |{{topPads}}
+  |  )
+  |  (bottom
+  |{{bottomPads}}
+  |  )
+  |)