Connected clocks | Exposed Master TL port

generators/chipyard/src/main/scala/DigitalTop.scala

@@ -29,6 +29,7 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem
   with chipyard.example.CanHavePeripheryStreamingFIR // Enables optionally adding the DSPTools FIR example widget
   with chipyard.example.CanHavePeripheryStreamingPassthrough // Enables optionally adding the DSPTools streaming-passthrough example widget
   with nvidia.blocks.dla.CanHavePeripheryNVDLA // Enables optionally having an NVDLA
+  with CanHaveMasterTLMemPort
 {
   override lazy val module = new DigitalTopModule(this)
 }
@@ -47,3 +48,42 @@ class DigitalTopModule[+L <: DigitalTop](l: L) extends ChipyardSystemModule(l)
   with chipyard.example.CanHavePeripheryGCDModuleImp
   with freechips.rocketchip.util.DontTouch
 // DOC include end: DigitalTop
+
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.tilelink._
+
+/** Adds a TileLink port to the system intended to master an MMIO device bus */
+trait CanHaveMasterTLMemPort { this: BaseSubsystem =>
+  private val memPortParamsOpt = p(ExtMem)
+  private val portName = "tl_mem"
+  private val device = new MemoryDevice
+  private val idBits = memPortParamsOpt.map(_.master.idBits).getOrElse(1)
+
+  val memTLNode = TLManagerNode(memPortParamsOpt.map({ case MemoryPortParams(memPortParams, nMemoryChannels) =>
+    Seq.tabulate(nMemoryChannels) { channel =>
+      val base = AddressSet.misaligned(memPortParams.base, memPortParams.size)
+      val filter = AddressSet(channel * mbus.blockBytes, ~((nMemoryChannels-1) * mbus.blockBytes))
+
+      TLSlavePortParameters.v1(
+        managers = Seq(TLSlaveParameters.v1(
+          address            = base.flatMap(_.intersect(filter)),
+          resources          = device.reg,
+          regionType         = RegionType.UNCACHED, // cacheable
+          executable         = true,
+          supportsGet        = TransferSizes(1, mbus.blockBytes),
+          supportsPutFull    = TransferSizes(1, mbus.blockBytes),
+          supportsPutPartial = TransferSizes(1, mbus.blockBytes))),
+        beatBytes = memPortParams.beatBytes)
+    }
+  }).toList.flatten)
+
+  mbus.coupleTo(s"memory_controller_port_named_$portName") {
+    (memTLNode
+      :*= TLBuffer()
+      :*= TLSourceShrinker(1 << idBits)
+      :*= TLWidthWidget(mbus.beatBytes)
+      :*= _)
+  }
+
+  val mem_tl = InModuleBody { memTLNode.makeIOs() }
+}

generators/chipyard/src/main/scala/System.scala

@@ -23,7 +23,6 @@ import freechips.rocketchip.util.{DontTouch}
  */
 class ChipyardSystem(implicit p: Parameters) extends ChipyardSubsystem
   with HasAsyncExtInterrupts
-  with CanHaveMasterAXI4MemPort
   with CanHaveMasterAXI4MMIOPort
   with CanHaveSlaveAXI4Port
 {