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Connected clocks | Exposed Master TL port

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This commit is contained in:
abejgonzalez
2020-09-15 12:58:58 -07:00
parent 72c0f4b3d3
commit f1b40d51af
6 changed files with 159 additions and 46 deletions
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94
fpga/src/main/scala/vcu118/TestHarness.scala
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@@ -4,7 +4,8 @@ import chisel3._
import chisel3.experimental.{Analog, IO}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.config.{Parameters}
import freechips.rocketchip.config.{Parameters, Field}
import freechips.rocketchip.subsystem.{ExtMem, BaseSubsystem}
import sifive.fpgashells.shell.xilinx._
import sifive.fpgashells.ip.xilinx._
@@ -16,20 +17,55 @@ import sifive.blocks.devices.spi._
import sifive.blocks.devices.i2c._
import sifive.blocks.devices.gpio._
import chipyard.fpga.vcu118.bringup._
import chipyard.fpga.vcu118.bringup.{BringupGPIOs, BringupUARTVCU118ShellPlacer, BringupSPIVCU118ShellPlacer, BringupI2CVCU118ShellPlacer, BringupGPIOVCU118ShellPlacer}
class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118Shell {
case object DUTFrequencyKey extends Field[Double](100.0)
class VCU118FPGATestHarness(override implicit val p: Parameters) extends ChipyardVCU118Shell {
def dp = designParameters
/*** Connect/Generate clocks ***/
// connect to the PLL that will generate multiple clocks
val harnessSysPLL = dp(PLLFactoryKey)()
sys_clock.get() match {
case Some(x : SysClockVCU118PlacedOverlay) => {
harnessSysPLL := x.node
}
}
// create and connect to the dutClock
val dutClock = ClockSinkNode(freqMHz = dp(DUTFrequencyKey))
val dutWrangler = LazyModule(new ResetWrangler)
val dutGroup = ClockGroup()
dutClock := dutWrangler.node := dutGroup := harnessSysPLL
InModuleBody {
topDesign.module match { case td: LazyModuleImp => {
td.clock := dutClock.in.head._1.clock
td.reset := dutClock.in.head._1.reset
}
}
}
// connect ref clock to dummy sink node
ref_clock.get() match {
case Some(x : RefClockVCU118PlacedOverlay) => {
val sink = ClockSinkNode(Seq(ClockSinkParameters()))
sink := x.node
}
}
/*** UART ***/
require(p(PeripheryUARTKey).size == 2)
require(dp(PeripheryUARTKey).size == 2)
// 1st UART goes to the VCU118 dedicated UART
// BundleBridgeSource is a was for Diplomacy to connect something from very deep in the design
// to somewhere much, much higher. For ex. tunneling trace from the tile to the very top level.
val io_uart_bb = BundleBridgeSource(() => (new UARTPortIO(p(PeripheryUARTKey).head)))
designParameters(UARTOverlayKey).head.place(UARTDesignInput(io_uart_bb))
val io_uart_bb = BundleBridgeSource(() => (new UARTPortIO(dp(PeripheryUARTKey).head)))
dp(UARTOverlayKey).head.place(UARTDesignInput(io_uart_bb))
InModuleBody {
topDesign.module match { case dutMod: HasVCU118PlatformIO =>
io_uart_bb.bundle <> dutMod.io_uart.head
@@ -38,10 +74,10 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S
// 2nd UART goes to the FMC UART
val uart_fmc = Overlay(UARTOverlayKey, new chipyard.fpga.vcu118.bringup.BringupUARTVCU118ShellPlacer(this, UARTShellInput()))
val uart_fmc = Overlay(UARTOverlayKey, new BringupUARTVCU118ShellPlacer(this, UARTShellInput()))
val io_uart_bb_2 = BundleBridgeSource(() => (new UARTPortIO(p(PeripheryUARTKey).last)))
designParameters(UARTOverlayKey).last.place(UARTDesignInput(io_uart_bb_2))
val io_uart_bb_2 = BundleBridgeSource(() => (new UARTPortIO(dp(PeripheryUARTKey).last)))
dp(UARTOverlayKey).last.place(UARTDesignInput(io_uart_bb_2))
InModuleBody {
topDesign.module match { case dutMod: HasVCU118PlatformIO =>
io_uart_bb_2.bundle <> dutMod.io_uart.last
@@ -49,12 +85,12 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S
}
/*** SPI ***/
require(p(PeripherySPIKey).size == 2)
require(dp(PeripherySPIKey).size == 2)
// 1st SPI goes to the VCU118 SDIO port
val io_spi_bb = BundleBridgeSource(() => (new SPIPortIO(p(PeripherySPIKey).head)))
val sdio_placed = designParameters(SPIOverlayKey).head.place(SPIDesignInput(p(PeripherySPIKey).head, io_spi_bb))
val io_spi_bb = BundleBridgeSource(() => (new SPIPortIO(dp(PeripherySPIKey).head)))
val sdio_placed = dp(SPIOverlayKey).head.place(SPIDesignInput(dp(PeripherySPIKey).head, io_spi_bb))
InModuleBody {
topDesign.module match { case dutMod: HasVCU118PlatformIO =>
io_spi_bb.bundle <> dutMod.io_spi.head
@@ -69,10 +105,10 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S
// 2nd SPI goes to the ADI port
val adi = Overlay(SPIOverlayKey, new chipyard.fpga.vcu118.bringup.BringupSPIVCU118ShellPlacer(this, SPIShellInput()))
val adi = Overlay(SPIOverlayKey, new BringupSPIVCU118ShellPlacer(this, SPIShellInput()))
val io_spi_bb_2 = BundleBridgeSource(() => (new SPIPortIO(p(PeripherySPIKey).last)))
val adi_placed = designParameters(SPIOverlayKey).last.place(SPIDesignInput(p(PeripherySPIKey).last, io_spi_bb_2))
val io_spi_bb_2 = BundleBridgeSource(() => (new SPIPortIO(dp(PeripherySPIKey).last)))
val adi_placed = dp(SPIOverlayKey).last.place(SPIDesignInput(dp(PeripherySPIKey).last, io_spi_bb_2))
InModuleBody {
topDesign.module match { case dutMod: HasVCU118PlatformIO =>
io_spi_bb_2.bundle <> dutMod.io_spi.last
@@ -86,12 +122,12 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S
//}
/*** I2C ***/
require(p(PeripheryI2CKey).size == 1)
require(dp(PeripheryI2CKey).size == 1)
val i2c = Overlay(I2COverlayKey, new chipyard.fpga.vcu118.bringup.BringupI2CVCU118ShellPlacer(this, I2CShellInput()))
val i2c = Overlay(I2COverlayKey, new BringupI2CVCU118ShellPlacer(this, I2CShellInput()))
val io_i2c_bb = BundleBridgeSource(() => (new I2CPort))
designParameters(I2COverlayKey).head.place(I2CDesignInput(io_i2c_bb))
dp(I2COverlayKey).head.place(I2CDesignInput(io_i2c_bb))
InModuleBody {
topDesign.module match { case dutMod: HasVCU118PlatformIO =>
io_i2c_bb.bundle <> dutMod.io_i2c.head
@@ -99,14 +135,14 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S
}
/*** GPIO ***/
val gpio = Seq.tabulate(p(PeripheryGPIOKey).size)(i => {
val gpio = Seq.tabulate(dp(PeripheryGPIOKey).size)(i => {
val maxGPIOSupport = 32
val names = BringupGPIOs.names.slice(maxGPIOSupport*i, maxGPIOSupport*(i+1))
Overlay(GPIOOverlayKey, new chipyard.fpga.vcu118.bringup.BringupGPIOVCU118ShellPlacer(this, GPIOShellInput(), names))
Overlay(GPIOOverlayKey, new BringupGPIOVCU118ShellPlacer(this, GPIOShellInput(), names))
})
val io_gpio_bb = p(PeripheryGPIOKey).map { p => BundleBridgeSource(() => (new GPIOPortIO(p))) }
(designParameters(GPIOOverlayKey) zip p(PeripheryGPIOKey)).zipWithIndex.map { case ((placer, params), i) =>
val io_gpio_bb = dp(PeripheryGPIOKey).map { p => BundleBridgeSource(() => (new GPIOPortIO(p))) }
(dp(GPIOOverlayKey) zip dp(PeripheryGPIOKey)).zipWithIndex.map { case ((placer, params), i) =>
placer.place(GPIODesignInput(params, io_gpio_bb(i)))
}
InModuleBody {
@@ -116,5 +152,19 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S
}
}
}
/*** Experimental DDR ***/
//val ddrPlaced = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtMem).get.master.base, dutWrangler.node, harnessSysPLL))
//topDesign match { case lazyDut: VCU118Platform =>
// lazyDut.lazySystem match { case lazyDutWBus: BaseSubsystem =>
// lazyDutWBus {
// InModuleBody {
// ddrPlaced.overlayOutput.ddr := lazyDutWBus.mbus.toDRAMController(Some("xilinxvcu118mig"))()
// }
// }
// }
//}
}