Move System/Subsystem to utilities
This commit is contained in:
Jerry Zhao
@@ -1,108 +0,0 @@
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//******************************************************************************
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// Copyright (c) 2019 - 2019, The Regents of the University of California (Regents).
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// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
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//------------------------------------------------------------------------------
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package example
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import chisel3._
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import chisel3.internal.sourceinfo.{SourceInfo}
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.devices.tilelink._
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import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp}
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.diplomaticobjectmodel.model.{OMInterrupt}
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import freechips.rocketchip.diplomaticobjectmodel.logicaltree.{RocketTileLogicalTreeNode, LogicalModuleTree}
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import freechips.rocketchip.tile._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.interrupts._
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import freechips.rocketchip.util._
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import freechips.rocketchip.subsystem._
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import freechips.rocketchip.amba.axi4._
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import boom.common.{BoomTile, BoomTilesKey, BoomCrossingKey}
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trait HasBoomAndRocketTiles extends HasTiles
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with CanHavePeripheryPLIC
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with CanHavePeripheryCLINT
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with HasPeripheryDebug
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{ this: BaseSubsystem =>
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val module: HasBoomAndRocketTilesModuleImp
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protected val rocketTileParams = p(RocketTilesKey)
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protected val boomTileParams = p(BoomTilesKey)
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// crossing can either be per tile or global (aka only 1 crossing specified)
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private val rocketCrossings = perTileOrGlobalSetting(p(RocketCrossingKey), rocketTileParams.size)
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private val boomCrossings = perTileOrGlobalSetting(p(BoomCrossingKey), boomTileParams.size)
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// Make a tile and wire its nodes into the system,
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// according to the specified type of clock crossing.
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// Note that we also inject new nodes into the tile itself,
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// also based on the crossing type.
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val rocketTiles = rocketTileParams.zip(rocketCrossings).map { case (tp, crossing) =>
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val rocket = LazyModule(new RocketTile(tp, crossing, PriorityMuxHartIdFromSeq(rocketTileParams), logicalTreeNode))
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connectMasterPortsToSBus(rocket, crossing)
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connectSlavePortsToCBus(rocket, crossing)
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def treeNode: RocketTileLogicalTreeNode = new RocketTileLogicalTreeNode(rocket.rocketLogicalTree.getOMInterruptTargets)
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LogicalModuleTree.add(logicalTreeNode, rocket.rocketLogicalTree)
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rocket
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}
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val boomTiles = boomTileParams.zip(boomCrossings).map { case (tp, crossing) =>
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val boom = LazyModule(new BoomTile(tp, crossing, PriorityMuxHartIdFromSeq(boomTileParams), logicalTreeNode))
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connectMasterPortsToSBus(boom, crossing)
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connectSlavePortsToCBus(boom, crossing)
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def treeNode: RocketTileLogicalTreeNode = new RocketTileLogicalTreeNode(boom.rocketLogicalTree.getOMInterruptTargets)
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LogicalModuleTree.add(logicalTreeNode, boom.rocketLogicalTree)
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boom
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}
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// combine tiles and connect interrupts based on the order of harts
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val boomAndRocketTiles = (rocketTiles ++ boomTiles).sortWith(_.tileParams.hartId < _.tileParams.hartId).map {
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tile => {
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connectInterrupts(tile, Some(debug), clintOpt, plicOpt)
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tile
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}
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}
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def coreMonitorBundles = (rocketTiles map { t => t.module.core.rocketImpl.coreMonitorBundle}).toList ++
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(boomTiles map { t => t.module.core.coreMonitorBundle}).toList
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}
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trait HasBoomAndRocketTilesModuleImp extends HasTilesModuleImp
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with HasPeripheryDebugModuleImp
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{
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val outer: HasBoomAndRocketTiles
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}
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class Subsystem(implicit p: Parameters) extends BaseSubsystem
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with HasBoomAndRocketTiles
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{
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val tiles = boomAndRocketTiles
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override lazy val module = new SubsystemModuleImp(this)
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def getOMInterruptDevice(resourceBindingsMap: ResourceBindingsMap): Seq[OMInterrupt] = Nil
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}
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class SubsystemModuleImp[+L <: Subsystem](_outer: L) extends BaseSubsystemModuleImp(_outer)
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with HasResetVectorWire
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with HasBoomAndRocketTilesModuleImp
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{
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tile_inputs.zip(outer.hartIdList).foreach { case(wire, i) =>
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wire.hartid := i.U
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wire.reset_vector := global_reset_vector
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}
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// create file with boom params
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ElaborationArtefacts.add("""core.config""", outer.tiles.map(x => x.module.toString).mkString("\n"))
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}
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@@ -1,45 +0,0 @@
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//******************************************************************************
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// Copyright (c) 2019 - 2019, The Regents of the University of California (Regents).
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// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
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//------------------------------------------------------------------------------
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package example
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import chisel3._
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import freechips.rocketchip.config.{Parameters}
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import freechips.rocketchip.subsystem._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.devices.tilelink._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.util.{DontTouch}
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// ---------------------------------------------------------------------
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// Base system that uses the debug test module (dtm) to bringup the core
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// ---------------------------------------------------------------------
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/**
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* Base top with periphery devices and ports, and a BOOM + Rocket subsystem
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*/
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class System(implicit p: Parameters) extends Subsystem
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with HasHierarchicalBusTopology
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with HasAsyncExtInterrupts
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with CanHaveMasterAXI4MemPort
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with CanHaveMasterAXI4MMIOPort
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with CanHaveSlaveAXI4Port
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with HasPeripheryBootROM
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{
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override lazy val module = new SystemModule(this)
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}
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/**
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* Base top module implementation with periphery devices and ports, and a BOOM + Rocket subsystem
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*/
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class SystemModule[+L <: System](_outer: L) extends SubsystemModuleImp(_outer)
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with HasRTCModuleImp
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with HasExtInterruptsModuleImp
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with CanHaveMasterAXI4MemPortModuleImp
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with CanHaveMasterAXI4MMIOPortModuleImp
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with CanHaveSlaveAXI4PortModuleImp
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with HasPeripheryBootROMModuleImp
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with DontTouch
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@@ -10,6 +10,8 @@ import freechips.rocketchip.util.DontTouch
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import testchipip._
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import utilities.{System, SystemModule}
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import sifive.blocks.devices.gpio._
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// ------------------------------------
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