From 4c0314a46a2c93d8faae4914a8d226b616eea98e Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sun, 12 Mar 2023 11:19:37 -0700 Subject: [PATCH 1/4] Bump verilator --- conda-reqs/chipyard.yaml | 2 +- ...ements-riscv-tools-linux-64.conda-lock.yml | 200 ++++++++++-------- sims/verilator/Makefile | 2 +- 3 files changed, 114 insertions(+), 90 deletions(-) diff --git a/conda-reqs/chipyard.yaml b/conda-reqs/chipyard.yaml index 9396f3b9..511fd70d 100644 --- a/conda-reqs/chipyard.yaml +++ b/conda-reqs/chipyard.yaml @@ -89,7 +89,7 @@ dependencies: - graphviz - expect - dtc - - verilator==4.226 + - verilator==5.006 - screen - elfutils - libdwarf-dev==0.0.0.20190110_28_ga81397fc4 # from ucb-bar channel - using mainline libdwarf-feedstock diff --git a/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml b/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml index 673bc0f9..de819a23 100644 --- a/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml +++ b/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml @@ -19,7 +19,7 @@ metadata: - url: nodefaults used_env_vars: [] content_hash: - linux-64: c24ce91cc2acc7e81ada9fe14d2a5dc398fc977952ab8ab03b82a6d32de079b3 + linux-64: e51f9c0b2e38f85b5879f02e9ae73bc539026c4e9196d97447f2249e5a486d43 platforms: - linux-64 sources: @@ -1421,16 +1421,16 @@ package: - category: main dependencies: gmp: '>=6.2.1,<7.0a0' - libgcc-ng: '>=7.5.0' + libgcc-ng: '>=12' hash: - md5: ea9ebeddb066da8fad4a815e61b139be - sha256: d2d71ac6ed3b32f06b7db2691e0a1760016ce13fb0c50a9de6ed1ccc33e35ff3 + md5: 14d87bdff2cbd3b1179a29fb316ed743 + sha256: 03097f21c75b0936471809e533dbae44af9d9ae696ecf264d1a929fc9f9e4b83 manager: conda name: mpfr optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/mpfr-4.1.0-h9202a9a_1.tar.bz2 - version: 4.1.0 + url: https://conda.anaconda.org/conda-forge/linux-64/mpfr-4.2.0-hb012696_0.conda + version: 4.2.0 - category: main dependencies: libffi: '>=3.4.2,<3.5.0a0' @@ -3078,14 +3078,14 @@ package: dependencies: python: '>=3.7' hash: - md5: 5aec57dd42104f4916c397fe291f9697 - sha256: bf40dd7bde1902859517888f72802fbc97709af7675de78eec38a1cd73ab898a + md5: e18ed61c37145bb9b48d1d98801960f7 + sha256: a5c48b1fc7c89c5c937475e9434a63af7ce2e591f8e51afd56e3b2e232a9989d manager: conda name: setuptools optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/setuptools-67.5.1-pyhd8ed1ab_0.conda - version: 67.5.1 + url: https://conda.anaconda.org/conda-forge/noarch/setuptools-67.6.0-pyhd8ed1ab_0.conda + version: 67.6.0 - category: main dependencies: python: '>=3.6' @@ -3320,14 +3320,14 @@ package: dependencies: python: '>=3.7' hash: - md5: 2d93b130d148d7fc77e583677792fc6a - sha256: 70c57b5ac94cd32e78f1a2fa2c38572bfac85b901a6a99aa254a9e8e126c132d + md5: 43e7d9e50261fb11deb76e17d8431aac + sha256: f81eee64fcdfb379e27d01773b34041fbf7f9e86f33b157c9925d19e0a442452 manager: conda name: typing_extensions optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/typing_extensions-4.4.0-pyha770c72_0.tar.bz2 - version: 4.4.0 + url: https://conda.anaconda.org/conda-forge/noarch/typing_extensions-4.5.0-pyha770c72_0.conda + version: 4.5.0 - category: main dependencies: libgcc-ng: '>=12' @@ -3365,18 +3365,19 @@ package: gxx_impl_linux-64: '' libgcc-ng: '>=12' libstdcxx-ng: '>=12' - libzlib: '>=1.2.12,<1.3.0a0' + libzlib: '>=1.2.13,<1.3.0a0' make: '' perl: '' + python: '' hash: - md5: 41af6df1758bae89161daf268566384e - sha256: e2f2302d69c0d6928d95a1c699b5ef0b14e0243e78495734962c78136d2e6b9f + md5: 1a0130b3de431ee4dd26734a234a1cde + sha256: 12971e7e175a7dfb70d4afcf76e38d1ed21a979d49e215d439e7392de221a14d manager: conda name: verilator optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/verilator-4.226-he0ac6c6_1.tar.bz2 - version: '4.226' + url: https://conda.anaconda.org/conda-forge/linux-64/verilator-5.006-h07cc95c_1.conda + version: '5.006' - category: main dependencies: gettext: '>=0.21.1,<1.0a0' @@ -3523,6 +3524,19 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/noarch/zipp-3.15.0-pyhd8ed1ab_0.conda version: 3.15.0 +- category: main + dependencies: + python: '>=3.6' + typing_extensions: '>=4.0' + hash: + md5: 59c40397276a286241c65faec5e1be3c + sha256: be2dbd6710438fa48b83bf06841091227276ae545d145dfe5cb5149c6484e951 + manager: conda + name: aioitertools + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/noarch/aioitertools-0.11.0-pyhd8ed1ab_0.tar.bz2 + version: 0.11.0 - category: main dependencies: frozenlist: '>=1.1.0' @@ -4171,16 +4185,16 @@ package: version: 2.28.11.15 - category: main dependencies: - typing_extensions: 4.4.0 pyha770c72_0 + typing_extensions: 4.5.0 pyha770c72_0 hash: - md5: be969210b61b897775a0de63cd9e9026 - sha256: 6f129b1bc18d111dcf3abaec6fcf6cbee00f1b77bb42d0f0bc8d85f8faa65cf0 + md5: b3c594fde1a80a1fc3eb9cc4a5dfe392 + sha256: 6da5e15fa533620ae2e7aca9a7d16013eed3a73ac64c47d7c3bf3deec39b63b9 manager: conda name: typing-extensions optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/typing-extensions-4.4.0-hd8ed1ab_0.tar.bz2 - version: 4.4.0 + url: https://conda.anaconda.org/conda-forge/noarch/typing-extensions-4.5.0-hd8ed1ab_0.conda + version: 4.5.0 - category: main dependencies: libgcc-ng: '>=9.3.0' @@ -4416,20 +4430,19 @@ package: dependencies: attrs: '>=17.4.0' importlib-metadata: '' - importlib_resources: '>=1.4.0' - pkgutil-resolve-name: '>=1.3.10' - pyrsistent: '!=0.17.0,!=0.17.1,!=0.17.2,>=0.14.0' - python: '>=3.7' - typing_extensions: '' + pyrsistent: '>=0.14.0' + python: '>=3.6' + setuptools: '' + six: '>=1.11.0' hash: - md5: 723268a468177cd44568eb8f794e0d80 - sha256: 4f68a23430d1afc5c9b41c46fbac0ade33c0bf57a293c646bfdd6dc65350eada + md5: 66125e28711d8ffc04a207a2b170316d + sha256: d74a3ddd3c3dd9bd7b00110a196e3af90490c5660674f18bfd53a8fdf91de418 manager: conda name: jsonschema optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/jsonschema-4.17.3-pyhd8ed1ab_0.conda - version: 4.17.3 + url: https://conda.anaconda.org/conda-forge/noarch/jsonschema-3.2.0-pyhd8ed1ab_3.tar.bz2 + version: 3.2.0 - category: main dependencies: elfutils: '>=0.187,<0.188.0a0' @@ -4635,14 +4648,14 @@ package: types-awscrt: '' typing_extensions: '' hash: - md5: 1284ea7cf431f599298c3e86922cb6ef - sha256: 949071f4ffaada1a7df890a0eca82507446f427d913272bae109c39f42b03361 + md5: 038f7d8f0f0b7cae4aee87bfbd09bd06 + sha256: 4c3babde56c86a3d0f83add59002275f8e8fd328acf432377c86ceb82b693131 manager: conda name: botocore-stubs optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/botocore-stubs-1.29.87-pyhd8ed1ab_0.conda - version: 1.29.87 + url: https://conda.anaconda.org/conda-forge/noarch/botocore-stubs-1.29.88-pyhd8ed1ab_0.conda + version: 1.29.88 - category: main dependencies: clang-format: 15.0.7 default_had23c3d_1 @@ -4775,19 +4788,17 @@ package: version: 3.7.1 - category: main dependencies: - attrs: '>=19.2.0' - jsonschema: '>=4.0.0,<5.0.0' + jsonschema: '>=3.0.0,<5.0.0' python: '>=3.7' - rfc3339-validator: '' hash: - md5: 8b32c5ef540b6afe23ea8e75dd400fbb - sha256: 8e69b65ffdc0d71f5d924c34d8e45bb2ca169573db29ede1844a46a2c8e3a5d0 + md5: 277aff70bb1def188c9c016ba4564e23 + sha256: 0c2f971f86211f2b6db431de9d8ab4c9e38eed5422bd06f93cd8be3cbb882a2c manager: conda name: openapi-schema-validator optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/openapi-schema-validator-0.4.3-pyhd8ed1ab_0.conda - version: 0.4.3 + url: https://conda.anaconda.org/conda-forge/noarch/openapi-schema-validator-0.2.3-pyhd8ed1ab_0.tar.bz2 + version: 0.2.3 - category: main dependencies: alsa-lib: '>=1.2.8,<1.2.9.0a0' @@ -5024,22 +5035,20 @@ package: version: 2.54.4 - category: main dependencies: - importlib_resources: '>=5.8.0,<6.0.0' - jsonschema: '>=4.0.0,<5.0.0' - jsonschema-spec: '>=0.1.1,<0.2.0' - lazy-object-proxy: '>=1.7.1,<2.0.0' - openapi-schema-validator: '>=0.4.2,<0.5' + jsonschema: '>=3.2.0,<5.0.0' + openapi-schema-validator: '>=0.2.0,<0.3.0' python: '>=3.7' pyyaml: '>=5.1' + setuptools: '' hash: - md5: 243b7dc9b3e129a2e7d5f2ca690f337c - sha256: 3053d96adb90a7dd6002c1151531485d9973a94050139a233701c3c25f94e0ea + md5: 5ff3ff67d18fd4938c4ae38c3baf21bb + sha256: 11f24d36001aaba0a7197ff7b9a07ab943d05f969b13e5a9c4ffec13eca19cd0 manager: conda name: openapi-spec-validator optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/openapi-spec-validator-0.5.5-pyhd8ed1ab_0.conda - version: 0.5.5 + url: https://conda.anaconda.org/conda-forge/noarch/openapi-spec-validator-0.4.0-pyhd8ed1ab_1.tar.bz2 + version: 0.4.0 - category: main dependencies: cfgv: '>=2.0.0' @@ -5081,14 +5090,14 @@ package: pysocks: '>=1.5.6,<2.0,!=1.5.7' python: <4.0 hash: - md5: 01f33ad2e0aaf6b5ba4add50dad5ad29 - sha256: f2f09c44e47946ce631dbc9a8a79bb463ac0f4122aaafdbcc51f200a1e420ca6 + md5: 27db656619a55d727eaf5a6ece3d2fd6 + sha256: 213bdf6c3a5d721fa83b45d527d3ecd340f9547c0d6bbd0b8d9d746ec9a1fb4b manager: conda name: urllib3 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/urllib3-1.26.14-pyhd8ed1ab_0.conda - version: 1.26.14 + url: https://conda.anaconda.org/conda-forge/noarch/urllib3-1.26.15-pyhd8ed1ab_0.conda + version: 1.26.15 - category: main dependencies: jmespath: '>=0.7.1,<2.0.0' @@ -5096,14 +5105,14 @@ package: python-dateutil: '>=2.1,<3.0.0' urllib3: '>=1.25.4,<1.27' hash: - md5: 2b1918369bcec3f3ff8dc380c60dff99 - sha256: 15b4107b40b9c39b3ca3631acc64f9734c71a7f1ede4e3b9c28275a2f62c4777 + md5: 7aa03b260e0e7803fafc414707cac996 + sha256: 9c3f2b48b8b69e436f80c4b5bd716ba4410ea1fe5f851406916e43f3feca05df manager: conda name: botocore optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/botocore-1.29.87-pyhd8ed1ab_0.conda - version: 1.29.87 + url: https://conda.anaconda.org/conda-forge/noarch/botocore-1.29.88-pyhd8ed1ab_0.conda + version: 1.29.88 - category: main dependencies: cairo: '>=1.16.0,<2.0a0' @@ -5149,6 +5158,22 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/noarch/requests-2.28.2-pyhd8ed1ab_0.conda version: 2.28.2 +- category: main + dependencies: + aiohttp: '>=3.3.1' + aioitertools: '>=0.5.1' + botocore: '>=1.27.59,<1.27.60' + python: '>=3.6' + wrapt: '>=1.10.10' + hash: + md5: a3f48ea10883a5df371b895008b1ca4b + sha256: 76068553358b26c9c03be992cbe982a369d1e015a53700f092db92c784ce98a9 + manager: conda + name: aiobotocore + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/noarch/aiobotocore-2.4.2-pyhd8ed1ab_0.conda + version: 2.4.2 - category: main dependencies: botocore: '>=1.11.3' @@ -5347,7 +5372,7 @@ package: version: 5.1.1 - category: main dependencies: - botocore: 1.29.87 + botocore: 1.29.88 colorama: '>=0.2.5,<0.4.5' docutils: '>=0.10,<0.17' python: '>=3.9,<3.10.0a0' @@ -5356,29 +5381,29 @@ package: rsa: '>=3.1.2,<4.8' s3transfer: '>=0.6.0,<0.7.0' hash: - md5: e34597b1774f550f23cca3fb3ad44079 - sha256: b92577f1601b257e7fc64bef8e733a8be7ac2ce1602d53e05c4497902371ad3c + md5: e9c5b0e909628d74e4ce807bb2a7693f + sha256: 2c641bc5be23dc659180c46126cb509034c67e4e5d3f68dc286d06199459f57e manager: conda name: awscli optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/awscli-1.27.87-py39hf3d152e_0.conda - version: 1.27.87 + url: https://conda.anaconda.org/conda-forge/linux-64/awscli-1.27.88-py39hf3d152e_0.conda + version: 1.27.88 - category: main dependencies: - botocore: '>=1.29.87,<1.30.0' + botocore: '>=1.29.88,<1.30.0' jmespath: '>=0.7.1,<2.0.0' python: '>=3.7' s3transfer: '>=0.6.0,<0.7.0' hash: - md5: 81cc299ce1dec9d92f55163356553fbe - sha256: 4712065876e3303bda6b2995770f2a7c131f6184b4d372c055ba505f56c77b50 + md5: 6d9d3d9ed7d005bf4180948445cf15a7 + sha256: f073885ff0739d25e35d62aa202f44df59fa75beb95a247b0f041c4973964c4b manager: conda name: boto3 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/boto3-1.26.87-pyhd8ed1ab_0.conda - version: 1.26.87 + url: https://conda.anaconda.org/conda-forge/noarch/boto3-1.26.88-pyhd8ed1ab_0.conda + version: 1.26.88 - category: main dependencies: cachecontrol: 0.12.11 pyhd8ed1ab_1 @@ -5500,20 +5525,19 @@ package: version: 2.0.0 - category: main dependencies: - boto3: '>=1.19.5,<2' - jsonschema: '>=3.2,<5' - pydantic: ~=1.10.2 - python: '>=3.7' - typing_extensions: ~=4.4.0 + boto3: ~=1.5 + jsonschema: ~=3.2 + python: '>=3.6' + six: ~=1.15 hash: - md5: 1136b4bb3893069daeb272a3d6aecd7b - sha256: 9d9316f995fa2aedd97a8495b1a8b87265d3d8fc0771c8a0e51da7c3c1a0571c + md5: 6a8ad721f4edea85a40070c78f379dd4 + sha256: d9b2ff5fdf1e8de7cf80f2a14a7cb76c65c0bae18a2fe51700e6ed3c71fdb5b5 manager: conda name: aws-sam-translator optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/aws-sam-translator-1.60.1-pyhd8ed1ab_0.conda - version: 1.60.1 + url: https://conda.anaconda.org/conda-forge/noarch/aws-sam-translator-1.55.0-pyhd8ed1ab_0.conda + version: 1.55.0 - category: main dependencies: azure-core: '>=1.11.0,<2.0.0' @@ -5537,14 +5561,14 @@ package: python: '' typing_extensions: '' hash: - md5: 5a9a5263ff74eabd589aab692b8d56cf - sha256: 2f4a2d7918d6aa3256c9491ccd3786206c1329825c2b7a21c902b0cb77c82703 + md5: 0665225dcc452177ebf284917328c4c1 + sha256: b03ab85abbac40c456ae8447d8a03345f54a6c7690efc1e1cf687db0ace600b8 manager: conda name: boto3-stubs optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/boto3-stubs-1.26.87-pyhd8ed1ab_0.conda - version: 1.26.87 + url: https://conda.anaconda.org/conda-forge/noarch/boto3-stubs-1.26.88-pyhd8ed1ab_0.conda + version: 1.26.88 - category: main dependencies: cachecontrol-with-filecache: '>=0.12.9' @@ -5685,14 +5709,14 @@ package: werkzeug: <2.2.0,>=0.5 xmltodict: '' hash: - md5: 24a19f3ea233ebd0cc0b8e6e0bc5df58 - sha256: 55e3f4fd163518afd72e926d88011cc47933779c97523b4d64b3680f99bd787b + md5: 7b8eaea28d5c08c8539c3b35a07fe3d1 + sha256: 47f8f38a9eff042ebd7754fa6c36739021c0e6cdca1848cc4b0138cfc4043ace manager: conda name: moto optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/moto-4.1.3-pyhd8ed1ab_0.conda - version: 4.1.3 + url: https://conda.anaconda.org/conda-forge/noarch/moto-4.1.4-pyhd8ed1ab_0.conda + version: 4.1.4 - dependencies: {} hash: sha256: ae88eca3024bb34bb3430f964beab71226e761f51b912de5133470b649d82344 diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index d48da28e..a6b97a1e 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -92,7 +92,7 @@ HELP_COMPILATION_VARIABLES += \ ######################################################################################### # verilator/cxx binary and flags ######################################################################################### -VERILATOR := verilator --cc --exe +VERILATOR := verilator --cc --exe --timing #---------------------------------------------------------------------------------------- # user configs From 95349755b553b66554ce55825ddad8964dd89f92 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sun, 12 Mar 2023 12:51:31 -0700 Subject: [PATCH 2/4] Support TestDriver.v as top --- .../src/main/resources/csrc/emulator.cc | 394 ------------------ sims/common-sim-flags.mk | 14 + sims/vcs/Makefile | 4 +- vcs.mk => sims/vcs/vcs.mk | 13 +- sims/verilator/Makefile | 65 ++- vlsi/Makefile | 2 +- 6 files changed, 43 insertions(+), 449 deletions(-) delete mode 100644 generators/chipyard/src/main/resources/csrc/emulator.cc rename vcs.mk => sims/vcs/vcs.mk (82%) diff --git a/generators/chipyard/src/main/resources/csrc/emulator.cc b/generators/chipyard/src/main/resources/csrc/emulator.cc deleted file mode 100644 index 40b5a2fa..00000000 --- a/generators/chipyard/src/main/resources/csrc/emulator.cc +++ /dev/null @@ -1,394 +0,0 @@ -// See LICENSE.SiFive for license details. -// See LICENSE.Berkeley for license details. - -#if VM_TRACE -#include -#if CY_FST_TRACE -#include "verilated_fst_c.h" -#else -#include "verilated.h" -#include "verilated_vcd_c.h" -#endif // CY_FST_TRACE -#endif // VM_TRACE -#include -#include -#include "remote_bitbang.h" -#include -#include -#include -#include -#include -#include -#include - -// For option parsing, which is split across this file, Verilog, and -// FESVR's HTIF, a few external files must be pulled in. The list of -// files and what they provide is enumerated: -// -// $RISCV/include/fesvr/htif.h: -// defines: -// - HTIF_USAGE_OPTIONS -// - HTIF_LONG_OPTIONS_OPTIND -// - HTIF_LONG_OPTIONS -// $(ROCKETCHIP_DIR)/generated-src(-debug)?/$(CONFIG).plusArgs: -// defines: -// - PLUSARG_USAGE_OPTIONS -// variables: -// - static const char * verilog_plusargs - -extern tsi_t* tsi; -extern dtm_t* dtm; -extern remote_bitbang_t * jtag; - -static uint64_t trace_count = 0; -bool verbose = false; -bool done_reset = false; - -void handle_sigterm(int sig) -{ - dtm->stop(); -} - -double sc_time_stamp() -{ - return trace_count; -} - -static void usage(const char * program_name) -{ - printf("Usage: %s [EMULATOR OPTION]... [VERILOG PLUSARG]... [HOST OPTION]... BINARY [TARGET OPTION]...\n", - program_name); - fputs("\ -Run a BINARY on the Rocket Chip emulator.\n\ -\n\ -Mandatory arguments to long options are mandatory for short options too.\n\ -\n\ -EMULATOR OPTIONS\n\ - -c, --cycle-count Print the cycle count before exiting\n\ - +cycle-count\n\ - -h, --help Display this help and exit\n\ - -m, --max-cycles=CYCLES Kill the emulation after CYCLES\n\ - +max-cycles=CYCLES\n\ - -s, --seed=SEED Use random number seed SEED\n\ - -r, --rbb-port=PORT Use PORT for remote bit bang (with OpenOCD and GDB) \n\ - If not specified, a random port will be chosen\n\ - automatically.\n\ - -V, --verbose Enable all Chisel printfs (cycle-by-cycle info)\n\ - +verbose\n\ -", stdout); -#if VM_TRACE == 0 - fputs("\ -\n\ -EMULATOR DEBUG OPTIONS (only supported in debug build -- try `make debug`)\n", - stdout); -#endif - fputs("\ - -v, --vcd=FILE, Write vcd trace to FILE (or '-' for stdout)\n\ - -x, --dump-start=CYCLE Start VCD tracing at CYCLE\n\ - +dump-start\n\ -", stdout); - fputs("\n" PLUSARG_USAGE_OPTIONS, stdout); - fputs("\n" HTIF_USAGE_OPTIONS, stdout); - printf("\n" -"EXAMPLES\n" -" - run a bare metal test:\n" -" %s $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-add\n" -" - run a bare metal test showing cycle-by-cycle information:\n" -" %s +verbose $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-add 2>&1 | spike-dasm\n" -#if VM_TRACE -" - run a bare metal test to generate a VCD waveform:\n" -" %s -v rv64ui-p-add.vcd $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-add\n" -#endif -" - run an ELF (you wrote, called 'hello') using the proxy kernel:\n" -" %s pk hello\n", - program_name, program_name, program_name -#if VM_TRACE - , program_name -#endif - ); -} - -int main(int argc, char** argv) -{ - unsigned random_seed = (unsigned)time(NULL) ^ (unsigned)getpid(); - uint64_t max_cycles = -1; - int ret = 0; - bool print_cycles = false; - // Port numbers are 16 bit unsigned integers. - uint16_t rbb_port = 0; -#if VM_TRACE - const char* vcdfile_name = NULL; - FILE * vcdfile = NULL; - uint64_t start = 0; -#endif - int verilog_plusargs_legal = 1; - - int verilated_argc = 1; - char** verilated_argv = new char*[argc]; - verilated_argv[0] = argv[0]; - - opterr = 1; - - while (1) { - static struct option long_options[] = { - {"cycle-count", no_argument, 0, 'c' }, - {"help", no_argument, 0, 'h' }, - {"max-cycles", required_argument, 0, 'm' }, - {"seed", required_argument, 0, 's' }, - {"rbb-port", required_argument, 0, 'r' }, - {"verbose", no_argument, 0, 'V' }, - {"permissive", no_argument, 0, 'p' }, - {"permissive-off", no_argument, 0, 'o' }, -#if VM_TRACE - {"vcd", required_argument, 0, 'v' }, - {"dump-start", required_argument, 0, 'x' }, -#endif - HTIF_LONG_OPTIONS - }; - int option_index = 0; -#if VM_TRACE - int c = getopt_long(argc, argv, "-chm:s:r:v:Vx:po", long_options, &option_index); -#else - int c = getopt_long(argc, argv, "-chm:s:r:Vpo", long_options, &option_index); -#endif - if (c == -1) break; - retry: - switch (c) { - // Process long and short EMULATOR options - case '?': usage(argv[0]); return 1; - case 'c': print_cycles = true; break; - case 'h': usage(argv[0]); return 0; - case 'm': max_cycles = atoll(optarg); break; - case 's': random_seed = atoi(optarg); break; - case 'r': rbb_port = atoi(optarg); break; - case 'V': verbose = true; break; - case 'p': opterr = 0; break; - case 'o': opterr = 1; break; -#if VM_TRACE - case 'v': { - vcdfile_name = optarg; - vcdfile = strcmp(optarg, "-") == 0 ? stdout : fopen(optarg, "w"); - if (!vcdfile) { - std::cerr << "Unable to open " << optarg << " for VCD write\n"; - return 1; - } - break; - } - case 'x': start = atoll(optarg); break; -#endif - // Process legacy '+' EMULATOR arguments by replacing them with - // their getopt equivalents - case 1: { - std::string arg = optarg; - if (arg.substr(0, 1) != "+") { - optind--; - goto done_processing; - } - if (arg == "+verbose") - c = 'V'; - else if (arg.substr(0, 12) == "+max-cycles=") { - c = 'm'; - optarg = optarg+12; - } -#if VM_TRACE - else if (arg.substr(0, 12) == "+dump-start=") { - c = 'x'; - optarg = optarg+12; - } -#endif - else if (arg.substr(0, 12) == "+cycle-count") - c = 'c'; - else if (arg == "+permissive") - { - c = 'p'; - verilated_argv[verilated_argc++] = optarg; - } - else if (arg == "+permissive-off") - { - c = 'o'; - verilated_argv[verilated_argc++] = optarg; - } - // If we don't find a legacy '+' EMULATOR argument, it still could be - // a VERILOG_PLUSARG and not an error. - else if (verilog_plusargs_legal) { - const char ** plusarg = &verilog_plusargs[0]; - int legal_verilog_plusarg = 0; - while (*plusarg && (legal_verilog_plusarg == 0)){ - if (arg.substr(1, strlen(*plusarg)) == *plusarg) { - legal_verilog_plusarg = 1; - } - plusarg ++; - } - if (!legal_verilog_plusarg) { - verilog_plusargs_legal = 0; - } else { - c = 'P'; - } - goto retry; - } - // If we STILL don't find a legacy '+' argument, it still could be - // an HTIF (HOST) argument and not an error. If this is the case, then - // we're done processing EMULATOR and VERILOG arguments. - else { - static struct option htif_long_options [] = { HTIF_LONG_OPTIONS }; - struct option * htif_option = &htif_long_options[0]; - while (htif_option->name) { - if (arg.substr(1, strlen(htif_option->name)) == htif_option->name) { - optind--; - goto done_processing; - } - htif_option++; - } - if(opterr) { - std::cerr << argv[0] << ": invalid plus-arg (Verilog or HTIF) \"" - << arg << "\"\n"; - c = '?'; - } else { - c = 'P'; - } - } - goto retry; - } - case 'P': // Verilog PlusArg, add to the argument list for verilator environment - verilated_argv[verilated_argc++] = optarg; - break; - // Realize that we've hit HTIF (HOST) arguments or error out - default: - if (c >= HTIF_LONG_OPTIONS_OPTIND) { - optind--; - goto done_processing; - } - c = '?'; - goto retry; - } - } - -done_processing: - if (optind == argc) { - std::cerr << "No binary specified for emulator\n"; - usage(argv[0]); - return 1; - } - - // Copy remaining HTIF arguments (if any) and the binary file name into the verilator argument stack - while (optind < argc) verilated_argv[verilated_argc++] = argv[optind++]; - - if (verbose) - fprintf(stderr, "using random seed %u\n", random_seed); - - srand(random_seed); - srand48(random_seed); - - Verilated::randReset(2); - Verilated::commandArgs(verilated_argc, verilated_argv); - TEST_HARNESS *tile = new TEST_HARNESS; - -#if VM_TRACE - Verilated::traceEverOn(true); // Verilator must compute traced signals -#if CY_FST_TRACE - std::unique_ptr tfp(new VerilatedFstC); -#else - std::unique_ptr vcdfd(new VerilatedVcdFILE(vcdfile)); - std::unique_ptr tfp(new VerilatedVcdC(vcdfd.get())); -#endif // CY_FST_TRACE - if (vcdfile_name) { - tile->trace(tfp.get(), 99); // Trace 99 levels of hierarchy - tfp->open(vcdfile_name); - } -#endif // VM_TRACE - - // RocketChip currently only supports RBB port 0, so this needs to stay here - jtag = new remote_bitbang_t(rbb_port); - - signal(SIGTERM, handle_sigterm); - - bool dump; - // start reset off low so a rising edge triggers async reset - tile->reset = 0; - tile->clock = 0; - tile->eval(); - // reset for several cycles to handle pipelined reset - for (int i = 0; i < 100; i++) { - tile->reset = 1; - tile->clock = 0; - tile->eval(); -#if VM_TRACE - dump = tfp && trace_count >= start; - if (dump) - tfp->dump(static_cast(trace_count * 2)); -#endif - tile->clock = 1; - tile->eval(); -#if VM_TRACE - if (dump) - tfp->dump(static_cast(trace_count * 2 + 1)); -#endif - trace_count ++; - } - tile->reset = 0; - done_reset = true; - - do { - tile->clock = 0; - tile->eval(); -#if VM_TRACE - dump = tfp && trace_count >= start; - if (dump) - tfp->dump(static_cast(trace_count * 2)); -#endif - - tile->clock = 1; - tile->eval(); -#if VM_TRACE - if (dump) - tfp->dump(static_cast(trace_count * 2 + 1)); -#endif - trace_count++; - } - // for verilator multithreading. need to do 1 loop before checking if - // tsi exists, since tsi is created by verilated thread on the first - // serial_tick. - while ((!dtm || !dtm->done()) && - (!jtag || !jtag->done()) && - (!tsi || !tsi->done()) && - !tile->io_success && trace_count < max_cycles); - -#if VM_TRACE - if (tfp) - tfp->close(); - if (vcdfile) - fclose(vcdfile); -#endif - - if (dtm && dtm->exit_code()) - { - fprintf(stderr, "*** FAILED *** via dtm (code = %d, seed %d) after %ld cycles\n", dtm->exit_code(), random_seed, trace_count); - ret = dtm->exit_code(); - } - else if (tsi && tsi->exit_code()) - { - fprintf(stderr, "*** FAILED *** (code = %d, seed %d) after %ld cycles\n", tsi->exit_code(), random_seed, trace_count); - ret = tsi->exit_code(); - } - else if (jtag && jtag->exit_code()) - { - fprintf(stderr, "*** FAILED *** via jtag (code = %d, seed %d) after %ld cycles\n", jtag->exit_code(), random_seed, trace_count); - ret = jtag->exit_code(); - } - else if (trace_count == max_cycles) - { - fprintf(stderr, "*** FAILED *** via trace_count (timeout, seed %d) after %ld cycles\n", random_seed, trace_count); - ret = 2; - } - else if (verbose || print_cycles) - { - fprintf(stderr, "*** PASSED *** Completed after %ld cycles\n", trace_count); - } - - if (dtm) delete dtm; - if (tsi) delete tsi; - if (jtag) delete jtag; - if (tile) delete tile; - if (verilated_argv) delete[] verilated_argv; - return ret; -} diff --git a/sims/common-sim-flags.mk b/sims/common-sim-flags.mk index 0736b43c..c2ae022c 100644 --- a/sims/common-sim-flags.mk +++ b/sims/common-sim-flags.mk @@ -33,3 +33,17 @@ SIM_LDFLAGS = \ -lfesvr \ -ldramsim \ $(EXTRA_SIM_LDFLAGS) + +CLOCK_PERIOD ?= 1.0 +RESET_DELAY ?= 777.7 + +SIM_PREPROC_DEFINES = \ + +define+CLOCK_PERIOD=$(CLOCK_PERIOD) \ + +define+RESET_DELAY=$(RESET_DELAY) \ + +define+PRINTF_COND=$(TB).printf_cond \ + +define+STOP_COND=!$(TB).reset \ + +define+MODEL=$(MODEL) \ + +define+RANDOMIZE_MEM_INIT \ + +define+RANDOMIZE_REG_INIT \ + +define+RANDOMIZE_GARBAGE_ASSIGN \ + +define+RANDOMIZE_INVALID_ASSIGN diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index b6f11a80..fc0a9fdb 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -25,7 +25,7 @@ sim_prefix = simv sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG) sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug -include $(base_dir)/vcs.mk +include $(sim_dir)/vcs.mk .PHONY: default debug default: $(sim) @@ -56,7 +56,7 @@ include $(base_dir)/common.mk ######################################################################################### VCS = vcs -full64 -VCS_OPTS = $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) $(PREPROC_DEFINES) +VCS_OPTS = $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) $(SIM_PREPROC_DEFINES) $(VCS_PREPROC_DEFINES) ######################################################################################### # vcs build paths diff --git a/vcs.mk b/sims/vcs/vcs.mk similarity index 82% rename from vcs.mk rename to sims/vcs/vcs.mk index edd19f8c..31784ad9 100644 --- a/vcs.mk +++ b/sims/vcs/vcs.mk @@ -53,17 +53,8 @@ VCS_NONCC_OPTS = \ -debug_pp \ +incdir+$(GEN_COLLATERAL_DIR) -PREPROC_DEFINES = \ - +define+VCS \ - +define+CLOCK_PERIOD=$(CLOCK_PERIOD) \ - +define+RESET_DELAY=$(RESET_DELAY) \ - +define+PRINTF_COND=$(TB).printf_cond \ - +define+STOP_COND=!$(TB).reset \ - +define+MODEL=$(MODEL) \ - +define+RANDOMIZE_MEM_INIT \ - +define+RANDOMIZE_REG_INIT \ - +define+RANDOMIZE_GARBAGE_ASSIGN \ - +define+RANDOMIZE_INVALID_ASSIGN +VCS_PREPROC_DEFINES = \ + +define+VCS ifndef USE_VPD PREPROC_DEFINES += +define+FSDB diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index a6b97a1e..9e22821d 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -28,8 +28,6 @@ sim_prefix = simulator sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG) sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug -WAVEFORM_FLAG=-v$(sim_out_name).vcd - include $(base_dir)/sims/common-sim-flags.mk # If verilator seed unspecified, verilator uses srand as random seed @@ -47,23 +45,7 @@ debug: $(sim_debug) # simulaton requirements ######################################################################################### SIM_FILE_REQS += \ - $(CHIPYARD_RSRCS_DIR)/csrc/emulator.cc \ - $(ROCKETCHIP_RSRCS_DIR)/csrc/verilator.h \ - -# the following files are needed for emulator.cc to compile (even if they aren't part of the RTL build) -SIM_FILE_REQS += \ - $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/SimSerial.cc \ - $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/testchip_tsi.cc \ - $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/testchip_tsi.h \ - $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/SimDRAM.cc \ - $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm.h \ - $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm.cc \ - $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm_dramsim2.h \ - $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm_dramsim2.cc \ - $(ROCKETCHIP_RSRCS_DIR)/csrc/SimDTM.cc \ - $(ROCKETCHIP_RSRCS_DIR)/csrc/SimJTAG.cc \ - $(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.h \ - $(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.cc + $(ROCKETCHIP_RSRCS_DIR)/vsrc/TestDriver.v # copy files and add -FI for *.h files in *.f $(sim_files): $(SIM_FILE_REQS) $(ALL_MODS_FILELIST) | $(GEN_COLLATERAL_DIR) @@ -87,12 +69,15 @@ HELP_COMPILATION_VARIABLES += \ " 'all' if full verilator runtime profiling" \ " 'threads' if runtime thread profiling only" \ " VERILATOR_THREADS = how many threads the simulator will use (default 1)" \ -" VERILATOR_FST_MODE = enable FST waveform instead of VCD. use with debug build" +" USE_FST = set to '1' to build Verilator simulator to emit FST instead of VCD." + +HELP_SIMULATION_VARIABLES += \ +" USE_FST = set to '1' to run Verilator simulator emitting FST instead of VCD." ######################################################################################### # verilator/cxx binary and flags ######################################################################################### -VERILATOR := verilator --cc --exe --timing +VERILATOR := verilator --main --timing --cc --exe #---------------------------------------------------------------------------------------- # user configs @@ -107,10 +92,12 @@ RUNTIME_PROFILING_VFLAGS := $(if $(filter $(VERILATOR_PROFILE),all),\ VERILATOR_THREADS ?= 1 RUNTIME_THREADS := --threads $(VERILATOR_THREADS) --threads-dpi all -VERILATOR_FST_MODE ?= 0 -TRACING_OPTS := $(if $(filter $(VERILATOR_FST_MODE),0),\ +USE_FST ?= 0 +TRACING_OPTS := $(if $(filter $(USE_FST),0),\ --trace,--trace-fst --trace-threads 1) -TRACING_CFLAGS := $(if $(filter $(VERILATOR_FST_MODE),0),,-DCY_FST_TRACE) +# TODO: consider renaming +vcdfile in TestDriver.v to +waveformfile (or similar) +WAVEFORM_FLAG := +vcdfile=$(sim_out_name).$(if $(filter $(USE_FST),0),\ + vcd,fst) #---------------------------------------------------------------------------------------- # verilation configuration/optimization @@ -153,9 +140,8 @@ TIMESCALE_OPTS := $(shell verilator --version | perl -lne 'if (/(\d.\d+)/ && $$1 # see: https://github.com/ucb-bar/riscv-mini/issues/31 MAX_WIDTH_OPTS = $(shell verilator --version | perl -lne 'if (/(\d.\d+)/ && $$1 > 4.016) { print "--max-num-width 1048576"; }') -PREPROC_DEFINES := \ - +define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \ - +define+STOP_COND=\$$c\(\"done_reset\"\) +VERILATOR_PREPROC_DEFINES = \ + +define+VERILATOR VERILATOR_NONCC_OPTS = \ $(RUNTIME_PROFILING_VFLAGS) \ @@ -165,8 +151,9 @@ VERILATOR_NONCC_OPTS = \ -Wno-fatal \ $(TIMESCALE_OPTS) \ $(MAX_WIDTH_OPTS) \ - $(PREPROC_DEFINES) \ - --top-module $(VLOG_MODEL) \ + $(SIM_PREPROC_DEFINES) \ + $(VERILATOR_PREPROC_DEFINES) \ + --top-module $(TB) \ --vpi \ -f $(sim_common_files) @@ -176,12 +163,8 @@ VERILATOR_NONCC_OPTS = \ VERILATOR_CXXFLAGS = \ $(SIM_CXXFLAGS) \ $(RUNTIME_PROFILING_CFLAGS) \ - $(TRACING_CFLAGS) \ - -D__STDC_FORMAT_MACROS \ - -DTEST_HARNESS=V$(VLOG_MODEL) \ -DVERILATOR \ - -include $(build_dir)/$(long_name).plusArgs \ - -include $(GEN_COLLATERAL_DIR)/verilator.h + -include $(build_dir)/$(long_name).plusArgs VERILATOR_LDFLAGS = $(SIM_LDFLAGS) @@ -200,11 +183,11 @@ VERILATOR_OPTS = $(VERILATOR_CC_OPTS) $(VERILATOR_NONCC_OPTS) model_dir = $(build_dir)/$(long_name) model_dir_debug = $(build_dir)/$(long_name).debug -model_header = $(model_dir)/V$(VLOG_MODEL).h -model_header_debug = $(model_dir_debug)/V$(VLOG_MODEL).h +model_header = $(model_dir)/V$(TB).h +model_header_debug = $(model_dir_debug)/V$(TB).h -model_mk = $(model_dir)/V$(VLOG_MODEL).mk -model_mk_debug = $(model_dir_debug)/V$(VLOG_MODEL).mk +model_mk = $(model_dir)/V$(TB).mk +model_mk_debug = $(model_dir_debug)/V$(TB).mk ######################################################################################### # build makefile fragment that builds the verilator sim rules @@ -218,17 +201,17 @@ $(model_mk): $(sim_common_files) $(EXTRA_SIM_REQS) $(model_mk_debug): $(sim_common_files) $(EXTRA_SIM_REQS) rm -rf $(model_dir_debug) mkdir -p $(model_dir_debug) - $(VERILATOR) $(VERILATOR_OPTS) $(EXTRA_SIM_SOURCES) -o $(sim_debug) $(TRACING_OPTS) -Mdir $(model_dir_debug) -CFLAGS "-include $(model_header_debug)" + $(VERILATOR) $(VERILATOR_OPTS) +define+DEBUG $(EXTRA_SIM_SOURCES) -o $(sim_debug) $(TRACING_OPTS) -Mdir $(model_dir_debug) -CFLAGS "-include $(model_header_debug)" touch $@ ######################################################################################### # invoke make to make verilator sim rules ######################################################################################### $(sim): $(model_mk) $(dramsim_lib) - $(MAKE) VM_PARALLEL_BUILDS=1 -C $(model_dir) -f V$(VLOG_MODEL).mk + $(MAKE) VM_PARALLEL_BUILDS=1 -C $(model_dir) -f V$(TB).mk $(sim_debug): $(model_mk_debug) $(dramsim_lib) - $(MAKE) VM_PARALLEL_BUILDS=1 -C $(model_dir_debug) -f V$(VLOG_MODEL).mk + $(MAKE) VM_PARALLEL_BUILDS=1 -C $(model_dir_debug) -f V$(TB).mk ######################################################################################### # create a verilator vpd rule diff --git a/vlsi/Makefile b/vlsi/Makefile index 8259e7a6..a19e63fe 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -134,7 +134,7 @@ $(SYN_CONF): $(VLSI_RTL) ######################################################################################### # simulation and power input configuration ######################################################################################### -include $(base_dir)/vcs.mk +include $(base_dir)/sims/vcs/vcs.mk SIM_FILE_REQS += \ $(ROCKETCHIP_RSRCS_DIR)/vsrc/TestDriver.v From d4dcbe3297044b9d9d19d14ba214d2b2dfbb4150 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 14 Mar 2023 15:45:39 -0700 Subject: [PATCH 3/4] Static cast enums --- generators/ibex | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/ibex b/generators/ibex index 5a512227..771a4f4e 160000 --- a/generators/ibex +++ b/generators/ibex @@ -1 +1 @@ -Subproject commit 5a512227d8f6d2929cc354c02d40200002e661e5 +Subproject commit 771a4f4ee94bf7ad144b328775ac1ab011443a8a From e832667ccec09a3ff887a8942729577a3bca965b Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 9 May 2023 13:31:00 -0700 Subject: [PATCH 4/4] Bump Verilator --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 3ae68ec3..0c1a7a63 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 3ae68ec3076c010c633ded369fd3874ec2e5e557 +Subproject commit 0c1a7a63396fa213d22ff218e00acc0594e303a8