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update docs to reflect new tutorial example, remove old dummy DCO stuff

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This commit is contained in:
Harrison Liew
2021-06-06 21:17:55 -07:00
parent a7214e671c
commit f08b22885a
9 changed files with 60 additions and 756 deletions
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3
vlsi/Makefile
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@@ -52,7 +52,7 @@ endif
# general rules
#########################################################################################
ALL_RTL = $(TOP_FILE) $(TOP_SMEMS_FILE)
extra_v_includes = $(build_dir)/EICG_wrapper.v $(vlsi_dir)/example.v
extra_v_includes = $(build_dir)/EICG_wrapper.v
ifneq ($(CUSTOM_VLOG), )
VLSI_RTL = $(CUSTOM_VLOG)
VLSI_BB = /dev/null
@@ -162,6 +162,7 @@ endif
$(SIM_DEBUG_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files)
mkdir -p $(dir $@)
mkdir -p $(output_dir)
echo "sim.inputs:" > $@
echo " defines: ['DEBUG']" >> $@
echo " defines_meta: 'append'" >> $@

65
vlsi/example.v
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@@ -1,65 +0,0 @@
// Sha3Accel w/ a blackbox (a dummy DCO) included inside
module Sha3AccelwBB( // @[:example.TestHarness.Sha3RocketConfig.fir@135905.2]
input clock, // @[:example.TestHarness.Sha3RocketConfig.fir@135906.4]
input reset, // @[:example.TestHarness.Sha3RocketConfig.fir@135907.4]
output io_cmd_ready, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
input io_cmd_valid, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
input [6:0] io_cmd_bits_inst_funct, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
input [63:0] io_cmd_bits_rs1, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
input [63:0] io_cmd_bits_rs2, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
input io_mem_req_ready, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
output io_mem_req_valid, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
output [39:0] io_mem_req_bits_addr, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
output [7:0] io_mem_req_bits_tag, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
output [4:0] io_mem_req_bits_cmd, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
output [63:0] io_mem_req_bits_data, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
input io_mem_resp_valid, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
input [7:0] io_mem_resp_bits_tag, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
input [63:0] io_mem_resp_bits_data, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
output io_busy, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
input [13:0] col_sel_b,
input [15:0] row_sel_b,
input [7:0] code_regulator,
input dither,
input sleep_b,
output dco_clock
);
Sha3Accel sha3 (
.clock(clock),
.reset(reset),
.io_cmd_ready(io_cmd_ready),
.io_cmd_valid(io_cmd_valid),
.io_cmd_bits_inst_funct(io_cmd_bits_inst_funct),
.io_cmd_bits_rs1(io_cmd_bits_rs1),
.io_cmd_bits_rs2(io_cmd_bits_rs2),
.io_mem_req_ready(io_mem_req_ready),
.io_mem_req_valid(io_mem_req_valid),
.io_mem_req_bits_addr(io_mem_req_bits_addr),
.io_mem_req_bits_tag(io_mem_req_bits_tag),
.io_mem_req_bits_cmd(io_mem_req_bits_cmd),
.io_mem_req_bits_data(io_mem_req_bits_data),
.io_mem_resp_valid(io_mem_resp_valid),
.io_mem_resp_bits_tag(io_mem_resp_bits_tag),
.io_mem_resp_bits_data(io_mem_resp_bits_data),
.io_busy(io_busy)
);
ExampleDCO dco (
.col_sel_b(col_sel_b),
.row_sel_b(row_sel_b),
.code_regulator(code_regulator),
.dither(dither),
.sleep_b(sleep_b),
.clock(dco_clock)
);
endmodule
module ExampleDCO (
input [13:0] col_sel_b,
input [15:0] row_sel_b,
input [7:0] code_regulator,
input dither,
input sleep_b,
output clock
);
endmodule

BIN
vlsi/extra_libraries/example/ExampleDCO.gds
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Binary file not shown.

377
vlsi/extra_libraries/example/ExampleDCO.lef
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@@ -1,377 +0,0 @@
VERSION 5.6 ;
BUSBITCHARS "[]" ;
DIVIDERCHAR "/" ;
MACRO ExampleDCO
CLASS BLOCK ;
ORIGIN 0 0 ;
FOREIGN ExampleDCO 0 0 ;
SIZE 123.936 BY 125.536 ;
SYMMETRY X Y ;
PIN VDD
DIRECTION INOUT ;
USE POWER ;
PORT
LAYER M5 ;
RECT 3.024 121.536 3.8 125.536 ;
END
END VDD
PIN VSS
DIRECTION INOUT ;
USE GROUND ;
PORT
LAYER M5 ;
RECT 1.728 121.536 2.5 125.536 ;
END
END VSS
PIN dither
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 0.384 1.2 0.768 ;
END
END dither
PIN row_sel_b[0]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 1.536 1.2 1.92 ;
END
END row_sel_b[0]
PIN row_sel_b[1]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 2.688 1.2 3.072 ;
END
END row_sel_b[1]
PIN row_sel_b[2]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 3.84 1.2 4.224 ;
END
END row_sel_b[2]
PIN row_sel_b[3]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 4.992 1.2 5.376 ;
END
END row_sel_b[3]
PIN row_sel_b[4]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 6.144 1.2 6.528 ;
END
END row_sel_b[4]
PIN row_sel_b[5]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 7.296 1.2 7.68 ;
END
END row_sel_b[5]
PIN row_sel_b[6]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 8.448 1.2 8.832 ;
END
END row_sel_b[6]
PIN row_sel_b[7]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 9.6 1.2 9.984 ;
END
END row_sel_b[7]
PIN row_sel_b[8]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 10.752 1.2 11.136 ;
END
END row_sel_b[8]
PIN row_sel_b[9]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 11.904 1.2 12.288 ;
END
END row_sel_b[9]
PIN row_sel_b[10]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 13.056 1.2 13.44 ;
END
END row_sel_b[10]
PIN row_sel_b[11]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 14.208 1.2 14.592 ;
END
END row_sel_b[11]
PIN row_sel_b[12]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 15.36 1.2 15.744 ;
END
END row_sel_b[12]
PIN row_sel_b[13]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 16.512 1.2 16.896 ;
END
END row_sel_b[13]
PIN row_sel_b[14]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 17.664 1.2 18.048 ;
END
END row_sel_b[14]
PIN row_sel_b[15]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 18.816 1.2 19.2 ;
END
END row_sel_b[15]
PIN col_sel_b[0]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 19.968 1.2 20.352 ;
END
END col_sel_b[0]
PIN col_sel_b[1]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 21.12 1.2 21.504 ;
END
END col_sel_b[1]
PIN col_sel_b[2]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 22.272 1.2 22.656 ;
END
END col_sel_b[2]
PIN col_sel_b[3]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 23.424 1.2 23.808 ;
END
END col_sel_b[3]
PIN col_sel_b[4]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 24.576 1.2 24.96 ;
END
END col_sel_b[4]
PIN col_sel_b[5]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 25.728 1.2 26.112 ;
END
END col_sel_b[5]
PIN col_sel_b[6]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 26.88 1.2 27.264 ;
END
END col_sel_b[6]
PIN col_sel_b[7]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 28.032 1.2 28.416 ;
END
END col_sel_b[7]
PIN col_sel_b[8]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 29.184 1.2 29.568 ;
END
END col_sel_b[8]
PIN col_sel_b[9]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 30.336 1.2 30.72 ;
END
END col_sel_b[9]
PIN col_sel_b[10]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 31.488 1.2 31.872 ;
END
END col_sel_b[10]
PIN col_sel_b[11]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 32.64 1.2 33.024 ;
END
END col_sel_b[11]
PIN col_sel_b[12]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 33.792 1.2 34.176 ;
END
END col_sel_b[12]
PIN col_sel_b[13]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 34.944 1.2 35.328 ;
END
END col_sel_b[13]
PIN code_regulator[0]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 36.096 1.2 36.48 ;
END
END code_regulator[0]
PIN code_regulator[1]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 37.248 1.2 37.632 ;
END
END code_regulator[1]
PIN code_regulator[2]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 38.4 1.2 38.784 ;
END
END code_regulator[2]
PIN code_regulator[3]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 39.552 1.2 39.936 ;
END
END code_regulator[3]
PIN code_regulator[4]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 40.704 1.2 41.088 ;
END
END code_regulator[4]
PIN code_regulator[5]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 41.856 1.2 42.24 ;
END
END code_regulator[5]
PIN code_regulator[6]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 43.008 1.2 43.392 ;
END
END code_regulator[6]
PIN code_regulator[7]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 44.16 1.2 44.544 ;
END
END code_regulator[7]
PIN sleep_b
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 45.312 1.2 45.696 ;
END
END sleep_b
PIN clock
DIRECTION OUTPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 122.736 0.384 123.936 0.768 ;
END
END clock
OBS
LAYER M1 ;
RECT 1.2 0.0 122.736 121.536 ;
LAYER M2 ;
RECT 1.2 0.0 122.736 121.536 ;
LAYER M3 ;
RECT 1.2 0.0 122.736 121.536 ;
LAYER M4 ;
RECT 1.2 0.0 122.736 121.536 ;
LAYER M5 ;
RECT 1.2 0.0 122.736 121.536 ;
LAYER M6 ;
RECT 1.2 0.0 122.736 121.536 ;
LAYER M7 ;
RECT 1.2 0.0 122.736 121.536 ;
LAYER M8 ;
RECT 1.2 0.0 122.736 121.536 ;
LAYER M9 ;
RECT 1.2 0.0 122.736 121.536 ;
END
END ExampleDCO
END LIBRARY

142
vlsi/extra_libraries/example/ExampleDCO_PVT_0P63V_100C.lib
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@@ -1,142 +0,0 @@
library (ExampleDCO_PVT_0P63V_100C) {
technology (cmos);
date : "Mon Sep 2 16:01:59 2019";
comment : "Generated by dotlibber.py";
revision : 0;
delay_model : table_lookup;
simulation : true;
capacitive_load_unit (1,pf);
voltage_unit : "1V";
current_unit : "1mA";
time_unit : "1ns";
pulling_resistance_unit : "1kohm";
nom_process : 1;
nom_temperature : 100;
nom_voltage : 0.630000;
voltage_map(VDD, 0.630000);
voltage_map(VSS, 0.000000);
operating_conditions("PVT_0P63V_100C") {
process : 1;
temperature : 100;
voltage : 0.630000;
}
default_operating_conditions : PVT_0P63V_100C;
lu_table_template (constraint_template_3x3) {
variable_1 : related_pin_transition;
variable_2 : constrained_pin_transition;
index_1 ("0.0002, 0.0004, 0.0006");
index_2 ("0.0002, 0.0004, 0.0006");
}
lu_table_template (delay_template_8x8) {
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1 ("0.0001, 0.0002, 0.0003, 0.0004, 0.0005, 0.0006, 0.0007, 0.0008");
index_2 ("0.0011, 0.0022, 0.0033, 0.0044, 0.0055, 0.0066, 0.0077, 0.0088");
}
type (bus_13_to_0) {
base_type : array ;
data_type : bit ;
bit_width : 14 ;
bit_from : 13 ;
bit_to : 0 ;
downto : true ;
}
type (bus_15_to_0) {
base_type : array ;
data_type : bit ;
bit_width : 16 ;
bit_from : 15 ;
bit_to : 0 ;
downto : true ;
}
type (bus_7_to_0) {
base_type : array ;
data_type : bit ;
bit_width : 8 ;
bit_from : 7 ;
bit_to : 0 ;
downto : true ;
}
cell (ExampleDCO) {
dont_use : true;
dont_touch : true;
is_macro_cell : true;
pg_pin (VDD) {
pg_type : primary_power;
voltage_name : VDD;
}
pg_pin (VSS) {
pg_type : primary_ground;
voltage_name : VSS;
}
pin (clock) {
direction : output;
clock : true;
max_capacitance : 0.02;
related_power_pin : VDD;
related_ground_pin : VSS;
}
bus ( col_sel_b ) {
bus_type : bus_13_to_0;
direction : input;
capacitance : 0.006;
max_transition : 0.04;
pin ( col_sel_b[13:0] ) {
related_power_pin : VDD;
related_ground_pin : VSS;
}
}
bus ( row_sel_b ) {
bus_type : bus_15_to_0;
direction : input;
capacitance : 0.006;
max_transition : 0.04;
pin ( row_sel_b[15:0] ) {
related_power_pin : VDD;
related_ground_pin : VSS;
}
}
bus ( code_regulator ) {
bus_type : bus_7_to_0;
direction : input;
capacitance : 0.006;
max_transition : 0.04;
pin ( code_regulator[7:0] ) {
related_power_pin : VDD;
related_ground_pin : VSS;
}
}
pin (dither) {
direction : input;
capacitance : 0.006;
max_transition : 0.04;
related_power_pin : VDD;
related_ground_pin : VSS;
}
pin (sleep_b) {
direction : input;
capacitance : 0.006;
max_transition : 0.04;
related_power_pin : VDD;
related_ground_pin : VSS;
}
}
}

142
vlsi/extra_libraries/example/ExampleDCO_PVT_0P77V_0C.lib
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@@ -1,142 +0,0 @@
library (ExampleDCO_PVT_0P77V_0C) {
technology (cmos);
date : "Mon Sep 2 16:01:59 2019";
comment : "Generated by dotlibber.py";
revision : 0;
delay_model : table_lookup;
simulation : true;
capacitive_load_unit (1,pf);
voltage_unit : "1V";
current_unit : "1mA";
time_unit : "1ns";
pulling_resistance_unit : "1kohm";
nom_process : 1;
nom_temperature : 0;
nom_voltage : 0.770000;
voltage_map(VDD, 0.770000);
voltage_map(VSS, 0.000000);
operating_conditions("PVT_0P77V_0C") {
process : 1;
temperature : 0;
voltage : 0.770000;
}
default_operating_conditions : PVT_0P77V_0C;
lu_table_template (constraint_template_3x3) {
variable_1 : related_pin_transition;
variable_2 : constrained_pin_transition;
index_1 ("0.0001, 0.0002, 0.0003");
index_2 ("0.0001, 0.0002, 0.0003");
}
lu_table_template (delay_template_8x8) {
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1 ("0.0003, 0.0004, 0.0005, 0.0006, 0.0007, 0.0008, 0.0009, 0.001");
index_2 ("0.0011, 0.0022, 0.0033, 0.0044, 0.0055, 0.0066, 0.0077, 0.0088");
}
type (bus_13_to_0) {
base_type : array ;
data_type : bit ;
bit_width : 14 ;
bit_from : 13 ;
bit_to : 0 ;
downto : true ;
}
type (bus_15_to_0) {
base_type : array ;
data_type : bit ;
bit_width : 16 ;
bit_from : 15 ;
bit_to : 0 ;
downto : true ;
}
type (bus_7_to_0) {
base_type : array ;
data_type : bit ;
bit_width : 8 ;
bit_from : 7 ;
bit_to : 0 ;
downto : true ;
}
cell (ExampleDCO) {
dont_use : true;
dont_touch : true;
is_macro_cell : true;
pg_pin (VDD) {
pg_type : primary_power;
voltage_name : VDD;
}
pg_pin (VSS) {
pg_type : primary_ground;
voltage_name : VSS;
}
pin (clock) {
direction : output;
clock : true;
max_capacitance : 0.02;
related_power_pin : VDD;
related_ground_pin : VSS;
}
bus ( col_sel_b ) {
bus_type : bus_13_to_0;
direction : input;
capacitance : 0.006;
max_transition : 0.04;
pin ( col_sel_b[13:0] ) {
related_power_pin : VDD;
related_ground_pin : VSS;
}
}
bus ( row_sel_b ) {
bus_type : bus_15_to_0;
direction : input;
capacitance : 0.006;
max_transition : 0.04;
pin ( row_sel_b[15:0] ) {
related_power_pin : VDD;
related_ground_pin : VSS;
}
}
bus ( code_regulator ) {
bus_type : bus_7_to_0;
direction : input;
capacitance : 0.006;
max_transition : 0.04;
pin ( code_regulator[7:0] ) {
related_power_pin : VDD;
related_ground_pin : VSS;
}
}
pin (dither) {
direction : input;
capacitance : 0.006;
max_transition : 0.04;
related_power_pin : VDD;
related_ground_pin : VSS;
}
pin (sleep_b) {
direction : input;
capacitance : 0.006;
max_transition : 0.04;
related_power_pin : VDD;
related_ground_pin : VSS;
}
}
}