update the docs up to tools

docs/Generators/Rocket-Chip.rst

@@ -2,7 +2,7 @@ Rocket Chip
 ===========
 
 Rocket Chip generator is an SoC generator developed at Berkeley and now supported by
-SiFive. Chipyard uses the Rocket Chip generator as the basis for producing a RISC-V SoC.
+`SiFive <https://www.sifive.com>`__. Chipyard uses the Rocket Chip generator as the basis for producing a RISC-V SoC.
 
 `Rocket Chip` is distinct from `Rocket core`, the in-order RISC-V CPU generator.
 Rocket Chip includes many parts of the SoC besides the CPU. Though Rocket Chip

docs/Generators/SHA3.rst

@@ -68,7 +68,7 @@ Using a SHA3 Accelerator
 ------------------------
 Since the SHA3 accelerator is designed as a RoCC accelerator,
 it can be mixed into a Rocket or BOOM core by overriding the
-BuildRoCC key. The configuration mixin is defined in the SHA3
+``BuildRoCC`` key. The configuration mixin is defined in the SHA3
 generator. An example configuration highlighting the use of
 this mixin is shown here:
 

docs/Generators/index.rst

@@ -9,7 +9,7 @@ A standard RTL design is essentially just a single instance of a design coming f
 However, by using meta-programming and parameter systems, generators can allow for integration of complex hardware designs in automated ways.
 The following pages introduce the generators integrated with the Chipyard framework.
 
-Chipyard bundles the source code for the generators, under the ``generators`` directory.
+Chipyard bundles the source code for the generators, under the ``generators/`` directory.
 It builds them from source each time (although the build system will cache results if they have not changed),
 so changes to the generators themselves will automatically be used when building with Chipyard and propagate to software simulation, FPGA-accelerated simulation, and VLSI flows.