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update the docs up to tools

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abejgonzalez
2019-10-07 20:29:14 -07:00
parent 73252f323b
commit ef3efa69ef
12 changed files with 32 additions and 23 deletions
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10
docs/Chipyard-Basics/Configs-Parameters-Mixins.rst
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@@ -103,7 +103,7 @@ implementation (ex. ``HasPeripherySerialModuleImp`` where ``Imp`` refers to impl
all the logical connections between generators and exchanges configuration information among them, while the
lazy module implementation performs the actual Chisel RTL elaboration.
In the MySoC example class, the "outer" ``MySoC`` instantiates the "inner"
In the ``MySoC`` example class, the "outer" ``MySoC`` instantiates the "inner"
``MySoCModuleImp`` as a lazy module implementation. This delays immediate elaboration
of the module until all logical connections are determined and all configuration information is exchanged.
The ``RocketSubsystem`` outer base class, as well as the
@@ -118,10 +118,10 @@ the ``SerialAdapter`` module, and instantiates queues.
In the test harness, the SoC is elaborated with
``val dut = Module(LazyModule(MySoC))``.
After elaboration, the result will be a MySoC module, which contains a
SerialAdapter module (among others).
After elaboration, the result will be a ``MySoC`` module, which contains a
``SerialAdapter`` module (among others).
From a high level, classes which extend LazyModule *must* reference
From a high level, classes which extend ``LazyModule`` *must* reference
their module implementation through ``lazy val module``, and they
*may* optionally reference other lazy modules (which will elaborate
as child modules in the module hierarchy). The "inner" modules
@@ -135,7 +135,7 @@ Mix-in
A mix-in is a Scala trait, which sets parameters for specific system components, as well as enabling instantiation and wiring of the relevant system components to system buses.
The naming convention for an additive mix-in is ``Has<YourMixin>``.
This is shown in the MySoC class where things such as ``HasPeripherySerial`` connect a RTL component to a bus and expose signals to the top-level.
This is shown in the ``MySoC`` class where things such as ``HasPeripherySerial`` connect a RTL component to a bus and expose signals to the top-level.
Additional References
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