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[firechip] Fix a uart multiclock bug

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This commit is contained in:
David Biancolin
2020-12-10 07:18:12 +00:00
parent 1787fda8c3
commit ee436c9b3f
1 changed files with 8 additions and 2 deletions
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10
generators/firechip/src/main/scala/BridgeBinders.scala
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@@ -4,12 +4,13 @@ package firesim.firesim
import chisel3._
import chisel3.experimental.annotate
import chisel3.util.experimental.BoringUtils
import freechips.rocketchip.config.{Field, Config, Parameters}
import freechips.rocketchip.diplomacy.{LazyModule}
import freechips.rocketchip.devices.debug.{Debug, HasPeripheryDebugModuleImp}
import freechips.rocketchip.amba.axi4.{AXI4Bundle}
import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPort, HasExtInterruptsModuleImp, BaseSubsystem, HasTilesModuleImp, ExtMem}
import freechips.rocketchip.subsystem._
import freechips.rocketchip.tile.{RocketTile}
import sifive.blocks.devices.uart._
@@ -86,7 +87,12 @@ class WithNICBridge extends OverrideHarnessBinder({
class WithUARTBridge extends OverrideHarnessBinder({
(system: HasPeripheryUARTModuleImp, th: FireSim, ports: Seq[UARTPortIO]) =>
ports.map { p => UARTBridge(th.harnessClock, p)(system.p) }; Nil
val uartSyncClock = Wire(Clock())
uartSyncClock := false.B.asClock
val pbusClockNode = system.outer.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(PBUS).fixedClockNode
val pbusClock = pbusClockNode.in.head._1.clock
BoringUtils.bore(pbusClock, Seq(uartSyncClock))
ports.map { p => UARTBridge(uartSyncClock, p)(system.p) }; Nil
})
class WithBlockDeviceBridge extends OverrideHarnessBinder({