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Formatting code to chisel standard

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- ran sbt scalafmtAll
  - lot of small formatting changes
- added test that code must stay formatted
  - part of github actions workflow
This commit is contained in:
chick
2021-08-16 15:35:22 -07:00
parent 4e9b44cad8
commit edb1537561
15 changed files with 145 additions and 99 deletions
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13
.github/workflows/run-ci.yml vendored
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@@ -24,3 +24,16 @@ jobs:
run: git submodule update --init run: git submodule update --init
- name: Test - name: Test
run: sbt test run: sbt test
doc:
name: Documentation and formatting
runs-on: ubuntu-latest
steps:
- name: Check Formatting
run: sbt scalafmtCheckAll
all_test_passed:
name: "all tests passed"
runs-on: ubuntu-latest
steps:
- run: echo Success

2
src/main/scala/barstools/macros/CostMetric.scala
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@@ -128,7 +128,7 @@ object DefaultMetric extends CostMetric with CostMetricCompanion {
} }
val maskPenalty = (memMask, libMask) match { val maskPenalty = (memMask, libMask) match {
case (None, Some(m)) => 0.001 case (None, Some(m)) => 0.001
case (_, _) => 0 case (_, _) => 0
} }
val depthCost = math.ceil(mem.src.depth.toDouble / lib.src.depth.toDouble) val depthCost = math.ceil(mem.src.depth.toDouble / lib.src.depth.toDouble)
val widthCost = math.ceil(memWidth.toDouble / lib.src.width.toDouble) val widthCost = math.ceil(memWidth.toDouble / lib.src.width.toDouble)

25
src/main/scala/barstools/macros/MacroCompiler.scala
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@@ -8,7 +8,7 @@
package barstools.macros package barstools.macros
import barstools.macros.Utils._ import barstools.macros.Utils._
import firrtl.Utils.{BoolType, one, zero} import firrtl.Utils.{one, zero, BoolType}
import firrtl.annotations._ import firrtl.annotations._
import firrtl.ir._ import firrtl.ir._
import firrtl.stage.{FirrtlSourceAnnotation, FirrtlStage, Forms, OutputFileAnnotation, RunFirrtlTransformAnnotation} import firrtl.stage.{FirrtlSourceAnnotation, FirrtlStage, Forms, OutputFileAnnotation, RunFirrtlTransformAnnotation}
@@ -109,16 +109,16 @@ object MacroCompilerAnnotation {
* @param forceSynflops Set of memories to force compiling as flops regardless of the mode * @param forceSynflops Set of memories to force compiling as flops regardless of the mode
*/ */
case class Params( case class Params(
mem: String, mem: String,
memFormat: Option[String], memFormat: Option[String],
lib: Option[String], lib: Option[String],
hammerIR: Option[String], hammerIR: Option[String],
costMetric: CostMetric, costMetric: CostMetric,
mode: CompilerMode, mode: CompilerMode,
useCompiler: Boolean, useCompiler: Boolean,
forceCompile: Set[String], forceCompile: Set[String],
forceSynflops: Set[String] forceSynflops: Set[String])
) extends Serializable extends Serializable
/** Create a MacroCompilerAnnotation. /** Create a MacroCompilerAnnotation.
* @param c Top-level circuit name (see class description) * @param c Top-level circuit name (see class description)
@@ -869,8 +869,7 @@ object MacroCompiler extends App {
case Some("conf") => case Some("conf") =>
filterForSRAM(readConfFromPath(params.get(Macros))).get.map(x => (new Macro(x)).blackbox) filterForSRAM(readConfFromPath(params.get(Macros))).get.map(x => (new Macro(x)).blackbox)
case _ => case _ =>
filterForSRAM(mdf.macrolib.Utils.readMDFFromPath(params.get(Macros))) filterForSRAM(mdf.macrolib.Utils.readMDFFromPath(params.get(Macros))).get
.get
.map(x => (new Macro(x)).blackbox) .map(x => (new Macro(x)).blackbox)
} }

2
src/main/scala/barstools/macros/SynFlops.scala
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@@ -3,7 +3,7 @@
package barstools.macros package barstools.macros
import barstools.macros.Utils._ import barstools.macros.Utils._
import firrtl.Utils.{zero, one} import firrtl.Utils.{one, zero}
import firrtl._ import firrtl._
import firrtl.ir._ import firrtl.ir._
import firrtl.passes.MemPortUtils.memPortField import firrtl.passes.MemPortUtils.memPortField

43
src/main/scala/barstools/tapeout/transforms/GenerateTopAndHarness.scala
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@@ -13,20 +13,20 @@ import logger.LazyLogging
// Requires two phases, one to collect modules below synTop in the hierarchy // Requires two phases, one to collect modules below synTop in the hierarchy
// and a second to remove those modules to generate the test harness // and a second to remove those modules to generate the test harness
private class GenerateTopAndHarness(annotations: AnnotationSeq) extends LazyLogging { private class GenerateTopAndHarness(annotations: AnnotationSeq) extends LazyLogging {
val synTop: Option[String] = annotations.collectFirst { case SynTopAnnotation(s) => s } val synTop: Option[String] = annotations.collectFirst { case SynTopAnnotation(s) => s }
val topFir: Option[String] = annotations.collectFirst { case TopFirAnnotation(s) => s } val topFir: Option[String] = annotations.collectFirst { case TopFirAnnotation(s) => s }
val harnessFir: Option[String] = annotations.collectFirst { case HarnessFirAnnotation(s) => s } val harnessFir: Option[String] = annotations.collectFirst { case HarnessFirAnnotation(s) => s }
val topAnnoOut: Option[String] = annotations.collectFirst { case TopAnnoOutAnnotation(s) => s } val topAnnoOut: Option[String] = annotations.collectFirst { case TopAnnoOutAnnotation(s) => s }
val harnessAnnoOut: Option[String] = annotations.collectFirst { case HarnessAnnoOutAnnotation(s) => s } val harnessAnnoOut: Option[String] = annotations.collectFirst { case HarnessAnnoOutAnnotation(s) => s }
val harnessTop: Option[String] = annotations.collectFirst { case HarnessTopAnnotation(h) => h } val harnessTop: Option[String] = annotations.collectFirst { case HarnessTopAnnotation(h) => h }
val harnessConf: Option[String] = annotations.collectFirst { case HarnessConfAnnotation(h) => h } val harnessConf: Option[String] = annotations.collectFirst { case HarnessConfAnnotation(h) => h }
val harnessOutput: Option[String] = annotations.collectFirst { case HarnessOutputAnnotation(h) => h } val harnessOutput: Option[String] = annotations.collectFirst { case HarnessOutputAnnotation(h) => h }
val topDotfOut: Option[String] = annotations.collectFirst { case TopDotfOutAnnotation(h) => h } val topDotfOut: Option[String] = annotations.collectFirst { case TopDotfOutAnnotation(h) => h }
val harnessDotfOut: Option[String] = annotations.collectFirst { case HarnessDotfOutAnnotation(h) => h } val harnessDotfOut: Option[String] = annotations.collectFirst { case HarnessDotfOutAnnotation(h) => h }
val annoFiles: List[String] = annotations.flatMap { val annoFiles: List[String] = annotations.flatMap {
case InputAnnotationFileAnnotation(f) => Some(f) case InputAnnotationFileAnnotation(f) => Some(f)
case _ => None case _ => None
}.toList }.toList
lazy val rootCircuitTarget = CircuitTarget(harnessTop.get) lazy val rootCircuitTarget = CircuitTarget(harnessTop.get)
@@ -36,11 +36,11 @@ private class GenerateTopAndHarness(annotations: AnnotationSeq) extends LazyLogg
// Dump firrtl and annotation files // Dump firrtl and annotation files
protected def dump( protected def dump(
circuit: Circuit, circuit: Circuit,
annotations: AnnotationSeq, annotations: AnnotationSeq,
firFile: Option[String], firFile: Option[String],
annoFile: Option[String] annoFile: Option[String]
): Unit = { ): Unit = {
firFile.foreach { firPath => firFile.foreach { firPath =>
val outputFile = new java.io.PrintWriter(firPath) val outputFile = new java.io.PrintWriter(firPath)
outputFile.write(circuit.serialize) outputFile.write(circuit.serialize)
@@ -49,9 +49,9 @@ private class GenerateTopAndHarness(annotations: AnnotationSeq) extends LazyLogg
annoFile.foreach { annoPath => annoFile.foreach { annoPath =>
val outputFile = new java.io.PrintWriter(annoPath) val outputFile = new java.io.PrintWriter(annoPath)
outputFile.write(JsonProtocol.serialize(annotations.filter(_ match { outputFile.write(JsonProtocol.serialize(annotations.filter(_ match {
case _: DeletedAnnotation => false case _: DeletedAnnotation => false
case _: EmittedComponent => false case _: EmittedComponent => false
case _: EmittedAnnotation[_] => false case _: EmittedAnnotation[_] => false
case _: FirrtlCircuitAnnotation => false case _: FirrtlCircuitAnnotation => false
case _ => true case _ => true
}))) })))
@@ -104,10 +104,10 @@ private class GenerateTopAndHarness(annotations: AnnotationSeq) extends LazyLogg
val generatorAnnotations = annotations val generatorAnnotations = annotations
.filterNot(_.isInstanceOf[OutputFileAnnotation]) .filterNot(_.isInstanceOf[OutputFileAnnotation])
.map { .map {
case ReplSeqMemAnnotation(i, _) => ReplSeqMemAnnotation(i, harnessConf.get) case ReplSeqMemAnnotation(i, _) => ReplSeqMemAnnotation(i, harnessConf.get)
case HarnessOutputAnnotation(s) => OutputFileAnnotation(s) case HarnessOutputAnnotation(s) => OutputFileAnnotation(s)
case anno => anno case anno => anno
} ++ harnessAnnos } ++ harnessAnnos
val annos = new FirrtlStage().execute(Array.empty, generatorAnnotations) val annos = new FirrtlStage().execute(Array.empty, generatorAnnotations)
annos.collectFirst { case FirrtlCircuitAnnotation(circuit) => circuit } match { annos.collectFirst { case FirrtlCircuitAnnotation(circuit) => circuit } match {
@@ -119,7 +119,6 @@ private class GenerateTopAndHarness(annotations: AnnotationSeq) extends LazyLogg
} }
} }
object GenerateTop extends StageMain(new TapeoutStage(doHarness = false)) object GenerateTop extends StageMain(new TapeoutStage(doHarness = false))
object GenerateTopAndHarness extends StageMain(new TapeoutStage(doHarness = true)) object GenerateTopAndHarness extends StageMain(new TapeoutStage(doHarness = true))

61
src/main/scala/barstools/tapeout/transforms/ReParentCircuit.scala
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@@ -34,33 +34,42 @@ class ReParentCircuit extends Transform with DependencyAPIMigration {
rmap rmap
} }
val newAnnotations = newTopName.map({ topName => val newAnnotations = newTopName
// Update InstanceTargets and ReferenceTargets .map({ topName =>
// Yes, these are identical functions, but the copy methods force separate implementations // Update InstanceTargets and ReferenceTargets
def updateInstance(t: InstanceTarget): Option[InstanceTarget] = { // Yes, these are identical functions, but the copy methods force separate implementations
val idx = t.path.lastIndexWhere(_._2.value == topName) def updateInstance(t: InstanceTarget): Option[InstanceTarget] = {
if (idx == -1) Some(t.copy(circuit=topName)) else Some(t.copy(circuit=topName, module=topName, path=t.path.drop(idx+1))) val idx = t.path.lastIndexWhere(_._2.value == topName)
} if (idx == -1) Some(t.copy(circuit = topName))
def updateReference(t: ReferenceTarget): Option[ReferenceTarget] = { else Some(t.copy(circuit = topName, module = topName, path = t.path.drop(idx + 1)))
val idx = t.path.lastIndexWhere(_._2.value == topName) }
if (idx == -1) Some(t.copy(circuit=topName)) else Some(t.copy(circuit=topName, module=topName, path=t.path.drop(idx+1))) def updateReference(t: ReferenceTarget): Option[ReferenceTarget] = {
} val idx = t.path.lastIndexWhere(_._2.value == topName)
if (idx == -1) Some(t.copy(circuit = topName))
else Some(t.copy(circuit = topName, module = topName, path = t.path.drop(idx + 1)))
}
AnnotationSeq(state.annotations.toSeq.map({ AnnotationSeq(
case x: SingleTargetAnnotation[InstanceTarget] if x.target.isInstanceOf[InstanceTarget] => state.annotations.toSeq
updateInstance(x.target).map(y => x.duplicate(y)) .map({
case x: SingleTargetAnnotation[ReferenceTarget] if x.target.isInstanceOf[ReferenceTarget] => case x: SingleTargetAnnotation[InstanceTarget] if x.target.isInstanceOf[InstanceTarget] =>
updateReference(x.target).map(y => x.duplicate(y)) updateInstance(x.target).map(y => x.duplicate(y))
case x: MultiTargetAnnotation => case x: SingleTargetAnnotation[ReferenceTarget] if x.target.isInstanceOf[ReferenceTarget] =>
val newTargets: Seq[Seq[Option[Target]]] = x.targets.map(_.map({ updateReference(x.target).map(y => x.duplicate(y))
case y: InstanceTarget => updateInstance(y) case x: MultiTargetAnnotation =>
case y: ReferenceTarget => updateReference(y) val newTargets: Seq[Seq[Option[Target]]] = x.targets.map(_.map({
case y => Some(y) case y: InstanceTarget => updateInstance(y)
})) case y: ReferenceTarget => updateReference(y)
if (newTargets.flatten.forall(_.isDefined)) Some(x.duplicate(newTargets.map(_.map(_.get)))) else None case y => Some(y)
case x => Some(x) }))
}).filter(_.isDefined).map(_.get)) if (newTargets.flatten.forall(_.isDefined)) Some(x.duplicate(newTargets.map(_.map(_.get)))) else None
}).getOrElse(state.annotations) case x => Some(x)
})
.filter(_.isDefined)
.map(_.get)
)
})
.getOrElse(state.annotations)
state.copy(circuit = newCircuit, renames = mainRename, annotations = newAnnotations) state.copy(circuit = newCircuit, renames = mainRename, annotations = newAnnotations)
} }

2
src/main/scala/barstools/tapeout/transforms/RemoveUnusedModules.scala
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@@ -23,7 +23,7 @@ class RemoveUnusedModules extends Transform with DependencyAPIMigration {
def execute(state: CircuitState): CircuitState = { def execute(state: CircuitState): CircuitState = {
val modulesByName = state.circuit.modules.map { val modulesByName = state.circuit.modules.map {
case m: Module => (m.name, Some(m)) case m: Module => (m.name, Some(m))
case m: ExtModule => (m.name, None) case m: ExtModule => (m.name, None)
}.toMap }.toMap

1
src/main/scala/barstools/tapeout/transforms/stage/TapeoutStage.scala
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@@ -178,4 +178,3 @@ class TapeoutStage(doHarness: Boolean) extends Stage {
annotations annotations
} }
} }

2
src/main/scala/barstools/tapeout/transforms/utils/FileUtils.scala
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@@ -2,7 +2,7 @@
package barstools.tapeout.transforms.utils package barstools.tapeout.transforms.utils
import chisel3.experimental.{ChiselAnnotation, annotate} import chisel3.experimental.{annotate, ChiselAnnotation}
import firrtl._ import firrtl._
import firrtl.annotations._ import firrtl.annotations._
import firrtl.stage.Forms import firrtl.stage.Forms

2
src/main/scala/mdf/macrolib/Utils.scala
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@@ -45,7 +45,7 @@ object Utils {
} catch { } catch {
case f: FileNotFoundException => case f: FileNotFoundException =>
println(s"FILE NOT FOUND $p in dir ${os.pwd}") println(s"FILE NOT FOUND $p in dir ${os.pwd}")
throw f throw f
} }
} }
} }

1
src/test/scala/barstools/macros/CostFunction.scala
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@@ -2,7 +2,6 @@ package barstools.macros
import mdf.macrolib.SRAMMacro import mdf.macrolib.SRAMMacro
/** Tests to check that the cost function mechanism is working properly. */ /** Tests to check that the cost function mechanism is working properly. */
/** A test metric that simply favours memories with smaller widths, to test that /** A test metric that simply favours memories with smaller widths, to test that

3
src/test/scala/barstools/macros/SpecificExamples.scala
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@@ -187,7 +187,8 @@ class BOOMTest extends MacroCompilerSpec with HasSRAMGenerator {
override val libPrefix = "src/test/resources" override val libPrefix = "src/test/resources"
val memSRAMs = mdf.macrolib.Utils.readMDFFromString(""" val memSRAMs = mdf.macrolib.Utils
.readMDFFromString("""
[ { [ {
"type" : "sram", "type" : "sram",
"name" : "_T_182_ext", "name" : "_T_182_ext",

18
src/test/scala/barstools/tapeout/transforms/GenerateSpec.scala
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@@ -42,10 +42,10 @@ class ToBeMadeExternal extends MultiIOModule {
class GenerateExampleTester extends MultiIOModule { class GenerateExampleTester extends MultiIOModule {
val success = IO(Output(Bool())) val success = IO(Output(Bool()))
val mod = Module(new GenerateExampleModule) val mod = Module(new GenerateExampleModule)
mod.in := 1.U mod.in := 1.U
val mod2 = Module(new ToBeMadeExternal) val mod2 = Module(new ToBeMadeExternal)
mod2.in := 1.U mod2.in := 1.U
val reg = RegInit(0.U(8.W)) val reg = RegInit(0.U(8.W))
@@ -91,10 +91,14 @@ class GenerateSpec extends AnyFreeSpec {
val targetDir = "test_run_dir/generate_spec" val targetDir = "test_run_dir/generate_spec"
generateTestData(targetDir) generateTestData(targetDir)
GenerateTop.main(Array( GenerateTop.main(
"-i", s"$targetDir/GenerateExampleTester.fir", Array(
"-o", s"$targetDir/GenerateExampleTester.v" "-i",
)) s"$targetDir/GenerateExampleTester.fir",
new File(s"$targetDir/GenerateExampleTester.v").exists() should be (true) "-o",
s"$targetDir/GenerateExampleTester.v"
)
)
new File(s"$targetDir/GenerateExampleTester.v").exists() should be(true)
} }
} }

66
src/test/scala/barstools/tapeout/transforms/GenerateTopSpec.scala
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@@ -19,9 +19,12 @@ class GenerateTopSpec extends AnyFreeSpec with Matchers {
GenerateTopAndHarness.main( GenerateTopAndHarness.main(
Array( Array(
"-i", s"$targetDir/ExampleModuleNeedsResetInverted.fir", "-i",
"-ll", "info", s"$targetDir/ExampleModuleNeedsResetInverted.fir",
"--log-file", transformListName "-ll",
"info",
"--log-file",
transformListName
) )
) )
@@ -47,26 +50,45 @@ class GenerateTopSpec extends AnyFreeSpec with Matchers {
GenerateTopAndHarness.main( GenerateTopAndHarness.main(
Array( Array(
"--target-dir", "test_run_dir/generate_top_spec", "--target-dir",
"-i", s"$targetDir/BlackBoxFloatTester.fir", "test_run_dir/generate_top_spec",
"-o", "chipyard.unittest.TestHarness.IceNetUnitTestConfig.top.v", "-i",
"-tho", "chipyard.unittest.TestHarness.IceNetUnitTestConfig.harness.v", s"$targetDir/BlackBoxFloatTester.fir",
"-i", "chipyard.unittest.TestHarness.IceNetUnitTestConfig.fir", "-o",
"--syn-top", "UnitTestSuite", "chipyard.unittest.TestHarness.IceNetUnitTestConfig.top.v",
"--harness-top", "TestHarness", "-tho",
"-faf", "chipyard.unittest.TestHarness.IceNetUnitTestConfig.anno.json", "chipyard.unittest.TestHarness.IceNetUnitTestConfig.harness.v",
"-tsaof", "chipyard.unittest.TestHarness.IceNetUnitTestConfig.top.anno.json", "-i",
"-tdf", "firrtl_black_box_resource_files.top.f", "chipyard.unittest.TestHarness.IceNetUnitTestConfig.fir",
"-tsf", "chipyard.unittest.TestHarness.IceNetUnitTestConfig.top.fir", "--syn-top",
"-thaof", "chipyard.unittest.TestHarness.IceNetUnitTestConfig.harness.anno.json", "UnitTestSuite",
"-hdf", "firrtl_black_box_resource_files.harness.f", "--harness-top",
"-thf", "chipyard.unittest.TestHarness.IceNetUnitTestConfig.harness.fir", "TestHarness",
"-faf",
"chipyard.unittest.TestHarness.IceNetUnitTestConfig.anno.json",
"-tsaof",
"chipyard.unittest.TestHarness.IceNetUnitTestConfig.top.anno.json",
"-tdf",
"firrtl_black_box_resource_files.top.f",
"-tsf",
"chipyard.unittest.TestHarness.IceNetUnitTestConfig.top.fir",
"-thaof",
"chipyard.unittest.TestHarness.IceNetUnitTestConfig.harness.anno.json",
"-hdf",
"firrtl_black_box_resource_files.harness.f",
"-thf",
"chipyard.unittest.TestHarness.IceNetUnitTestConfig.harness.fir",
"--infer-rw", "--infer-rw",
"--repl-seq-mem", "-c:TestHarness:-o:chipyard.unittest.TestHarness.IceNetUnitTestConfig.top.mems.conf", "--repl-seq-mem",
"-thconf", "chipyard.unittest.TestHarness.IceNetUnitTestConfig.harness.mems.conf", "-c:TestHarness:-o:chipyard.unittest.TestHarness.IceNetUnitTestConfig.top.mems.conf",
"-td", "test_run_dir/from-ci", "-thconf",
"-ll", "info", "chipyard.unittest.TestHarness.IceNetUnitTestConfig.harness.mems.conf",
"--log-file", logOutputName "-td",
"test_run_dir/from-ci",
"-ll",
"info",
"--log-file",
logOutputName
) )
) )

3
src/test/scala/barstools/tapeout/transforms/ResetInverterSpec.scala
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@@ -22,7 +22,8 @@ class ExampleModuleNeedsResetInverted extends Module with ResetInverter {
class ResetNSpec extends AnyFreeSpec with Matchers { class ResetNSpec extends AnyFreeSpec with Matchers {
"Inverting reset needs to be done throughout module in Chirrtl" in { "Inverting reset needs to be done throughout module in Chirrtl" in {
val chirrtl = (new ChiselStage).emitChirrtl(new ExampleModuleNeedsResetInverted, Array("--target-dir", "test_run_dir/reset_n_spec")) val chirrtl = (new ChiselStage)
.emitChirrtl(new ExampleModuleNeedsResetInverted, Array("--target-dir", "test_run_dir/reset_n_spec"))
chirrtl should include("input reset :") chirrtl should include("input reset :")
(chirrtl should not).include("input reset_n :") (chirrtl should not).include("input reset_n :")
(chirrtl should not).include("node reset = not(reset_n)") (chirrtl should not).include("node reset = not(reset_n)")