Formatting code to chisel standard

- ran sbt scalafmtAll
  - lot of small formatting changes
- added test that code must stay formatted
  - part of github actions workflow

.github/workflows/run-ci.yml

@@ -24,3 +24,16 @@ jobs:
         run: git submodule update --init
       - name: Test
         run: sbt test
+
+  doc:
+    name: Documentation and formatting
+    runs-on: ubuntu-latest
+    steps:
+      - name: Check Formatting
+        run: sbt scalafmtCheckAll
+
+  all_test_passed:
+    name: "all tests passed"
+    runs-on: ubuntu-latest
+    steps:
+      - run: echo Success

src/main/scala/barstools/macros/MacroCompiler.scala

@@ -8,7 +8,7 @@
 package barstools.macros
 
 import barstools.macros.Utils._
-import firrtl.Utils.{BoolType, one, zero}
+import firrtl.Utils.{one, zero, BoolType}
 import firrtl.annotations._
 import firrtl.ir._
 import firrtl.stage.{FirrtlSourceAnnotation, FirrtlStage, Forms, OutputFileAnnotation, RunFirrtlTransformAnnotation}
@@ -117,8 +117,8 @@ object MacroCompilerAnnotation {
     mode:          CompilerMode,
     useCompiler:   Boolean,
     forceCompile:  Set[String],
-                     forceSynflops: Set[String]
+    forceSynflops: Set[String])
-                   ) extends Serializable
+      extends Serializable
 
   /** Create a MacroCompilerAnnotation.
     * @param c Top-level circuit name (see class description)
@@ -869,8 +869,7 @@ object MacroCompiler extends App {
         case Some("conf") =>
           filterForSRAM(readConfFromPath(params.get(Macros))).get.map(x => (new Macro(x)).blackbox)
         case _ =>
-          filterForSRAM(mdf.macrolib.Utils.readMDFFromPath(params.get(Macros)))
+          filterForSRAM(mdf.macrolib.Utils.readMDFFromPath(params.get(Macros))).get
-            .get
             .map(x => (new Macro(x)).blackbox)
       }
 

src/main/scala/barstools/macros/SynFlops.scala

@@ -3,7 +3,7 @@
 package barstools.macros
 
 import barstools.macros.Utils._
-import firrtl.Utils.{zero, one}
+import firrtl.Utils.{one, zero}
 import firrtl._
 import firrtl.ir._
 import firrtl.passes.MemPortUtils.memPortField

src/main/scala/barstools/tapeout/transforms/GenerateTopAndHarness.scala

@@ -119,7 +119,6 @@ private class GenerateTopAndHarness(annotations: AnnotationSeq) extends LazyLogg
   }
 }
 
-
 object GenerateTop extends StageMain(new TapeoutStage(doHarness = false))
 
 object GenerateTopAndHarness extends StageMain(new TapeoutStage(doHarness = true))

src/main/scala/barstools/tapeout/transforms/ReParentCircuit.scala

@@ -34,19 +34,24 @@ class ReParentCircuit extends Transform with DependencyAPIMigration {
       rmap
     }
 
-    val newAnnotations = newTopName.map({ topName =>
+    val newAnnotations = newTopName
+      .map({ topName =>
         // Update InstanceTargets and ReferenceTargets
         // Yes, these are identical functions, but the copy methods force separate implementations
         def updateInstance(t: InstanceTarget): Option[InstanceTarget] = {
           val idx = t.path.lastIndexWhere(_._2.value == topName)
-        if (idx == -1) Some(t.copy(circuit=topName)) else Some(t.copy(circuit=topName, module=topName, path=t.path.drop(idx+1)))
+          if (idx == -1) Some(t.copy(circuit = topName))
+          else Some(t.copy(circuit = topName, module = topName, path = t.path.drop(idx + 1)))
         }
         def updateReference(t: ReferenceTarget): Option[ReferenceTarget] = {
           val idx = t.path.lastIndexWhere(_._2.value == topName)
-        if (idx == -1) Some(t.copy(circuit=topName)) else Some(t.copy(circuit=topName, module=topName, path=t.path.drop(idx+1)))
+          if (idx == -1) Some(t.copy(circuit = topName))
+          else Some(t.copy(circuit = topName, module = topName, path = t.path.drop(idx + 1)))
         }
 
-      AnnotationSeq(state.annotations.toSeq.map({
+        AnnotationSeq(
+          state.annotations.toSeq
+            .map({
               case x: SingleTargetAnnotation[InstanceTarget] if x.target.isInstanceOf[InstanceTarget] =>
                 updateInstance(x.target).map(y => x.duplicate(y))
               case x: SingleTargetAnnotation[ReferenceTarget] if x.target.isInstanceOf[ReferenceTarget] =>
@@ -59,8 +64,12 @@ class ReParentCircuit extends Transform with DependencyAPIMigration {
                 }))
                 if (newTargets.flatten.forall(_.isDefined)) Some(x.duplicate(newTargets.map(_.map(_.get)))) else None
               case x => Some(x)
-      }).filter(_.isDefined).map(_.get))
+            })
-    }).getOrElse(state.annotations)
+            .filter(_.isDefined)
+            .map(_.get)
+        )
+      })
+      .getOrElse(state.annotations)
 
     state.copy(circuit = newCircuit, renames = mainRename, annotations = newAnnotations)
   }

src/main/scala/barstools/tapeout/transforms/stage/TapeoutStage.scala

@@ -178,4 +178,3 @@ class TapeoutStage(doHarness: Boolean) extends Stage {
     annotations
   }
 }
-

src/main/scala/barstools/tapeout/transforms/utils/FileUtils.scala

@@ -2,7 +2,7 @@
 
 package barstools.tapeout.transforms.utils
 
-import chisel3.experimental.{ChiselAnnotation, annotate}
+import chisel3.experimental.{annotate, ChiselAnnotation}
 import firrtl._
 import firrtl.annotations._
 import firrtl.stage.Forms

src/test/scala/barstools/macros/CostFunction.scala

@@ -2,7 +2,6 @@ package barstools.macros
 
 import mdf.macrolib.SRAMMacro
 
-
 /** Tests to check that the cost function mechanism is working properly. */
 
 /** A test metric that simply favours memories with smaller widths, to test that

src/test/scala/barstools/macros/SpecificExamples.scala

@@ -187,7 +187,8 @@ class BOOMTest extends MacroCompilerSpec with HasSRAMGenerator {
 
   override val libPrefix = "src/test/resources"
 
-  val memSRAMs = mdf.macrolib.Utils.readMDFFromString("""
+  val memSRAMs = mdf.macrolib.Utils
+    .readMDFFromString("""
 [ {
   "type" : "sram",
   "name" : "_T_182_ext",

src/test/scala/barstools/tapeout/transforms/GenerateSpec.scala

@@ -91,10 +91,14 @@ class GenerateSpec extends AnyFreeSpec {
     val targetDir = "test_run_dir/generate_spec"
     generateTestData(targetDir)
 
-    GenerateTop.main(Array(
+    GenerateTop.main(
-      "-i", s"$targetDir/GenerateExampleTester.fir",
+      Array(
-      "-o", s"$targetDir/GenerateExampleTester.v"
+        "-i",
-    ))
+        s"$targetDir/GenerateExampleTester.fir",
+        "-o",
+        s"$targetDir/GenerateExampleTester.v"
+      )
+    )
     new File(s"$targetDir/GenerateExampleTester.v").exists() should be(true)
   }
 }

src/test/scala/barstools/tapeout/transforms/GenerateTopSpec.scala

@@ -19,9 +19,12 @@ class GenerateTopSpec extends AnyFreeSpec with Matchers {
 
       GenerateTopAndHarness.main(
         Array(
-          "-i", s"$targetDir/ExampleModuleNeedsResetInverted.fir",
+          "-i",
-          "-ll", "info",
+          s"$targetDir/ExampleModuleNeedsResetInverted.fir",
-          "--log-file", transformListName
+          "-ll",
+          "info",
+          "--log-file",
+          transformListName
         )
       )
 
@@ -47,26 +50,45 @@ class GenerateTopSpec extends AnyFreeSpec with Matchers {
 
     GenerateTopAndHarness.main(
       Array(
-        "--target-dir", "test_run_dir/generate_top_spec",
+        "--target-dir",
-        "-i", s"$targetDir/BlackBoxFloatTester.fir",
+        "test_run_dir/generate_top_spec",
-        "-o", "chipyard.unittest.TestHarness.IceNetUnitTestConfig.top.v",
+        "-i",
-        "-tho", "chipyard.unittest.TestHarness.IceNetUnitTestConfig.harness.v",
+        s"$targetDir/BlackBoxFloatTester.fir",
-        "-i", "chipyard.unittest.TestHarness.IceNetUnitTestConfig.fir",
+        "-o",
-        "--syn-top", "UnitTestSuite",
+        "chipyard.unittest.TestHarness.IceNetUnitTestConfig.top.v",
-        "--harness-top", "TestHarness",
+        "-tho",
-        "-faf", "chipyard.unittest.TestHarness.IceNetUnitTestConfig.anno.json",
+        "chipyard.unittest.TestHarness.IceNetUnitTestConfig.harness.v",
-        "-tsaof", "chipyard.unittest.TestHarness.IceNetUnitTestConfig.top.anno.json",
+        "-i",
-        "-tdf", "firrtl_black_box_resource_files.top.f",
+        "chipyard.unittest.TestHarness.IceNetUnitTestConfig.fir",
-        "-tsf", "chipyard.unittest.TestHarness.IceNetUnitTestConfig.top.fir",
+        "--syn-top",
-        "-thaof", "chipyard.unittest.TestHarness.IceNetUnitTestConfig.harness.anno.json",
+        "UnitTestSuite",
-        "-hdf", "firrtl_black_box_resource_files.harness.f",
+        "--harness-top",
-        "-thf", "chipyard.unittest.TestHarness.IceNetUnitTestConfig.harness.fir",
+        "TestHarness",
+        "-faf",
+        "chipyard.unittest.TestHarness.IceNetUnitTestConfig.anno.json",
+        "-tsaof",
+        "chipyard.unittest.TestHarness.IceNetUnitTestConfig.top.anno.json",
+        "-tdf",
+        "firrtl_black_box_resource_files.top.f",
+        "-tsf",
+        "chipyard.unittest.TestHarness.IceNetUnitTestConfig.top.fir",
+        "-thaof",
+        "chipyard.unittest.TestHarness.IceNetUnitTestConfig.harness.anno.json",
+        "-hdf",
+        "firrtl_black_box_resource_files.harness.f",
+        "-thf",
+        "chipyard.unittest.TestHarness.IceNetUnitTestConfig.harness.fir",
         "--infer-rw",
-        "--repl-seq-mem", "-c:TestHarness:-o:chipyard.unittest.TestHarness.IceNetUnitTestConfig.top.mems.conf",
+        "--repl-seq-mem",
-        "-thconf", "chipyard.unittest.TestHarness.IceNetUnitTestConfig.harness.mems.conf",
+        "-c:TestHarness:-o:chipyard.unittest.TestHarness.IceNetUnitTestConfig.top.mems.conf",
-        "-td", "test_run_dir/from-ci",
+        "-thconf",
-        "-ll", "info",
+        "chipyard.unittest.TestHarness.IceNetUnitTestConfig.harness.mems.conf",
-        "--log-file", logOutputName
+        "-td",
+        "test_run_dir/from-ci",
+        "-ll",
+        "info",
+        "--log-file",
+        logOutputName
       )
     )
 

src/test/scala/barstools/tapeout/transforms/ResetInverterSpec.scala

@@ -22,7 +22,8 @@ class ExampleModuleNeedsResetInverted extends Module with ResetInverter {
 
 class ResetNSpec extends AnyFreeSpec with Matchers {
   "Inverting reset needs to be done throughout module in Chirrtl" in {
-    val chirrtl = (new ChiselStage).emitChirrtl(new ExampleModuleNeedsResetInverted, Array("--target-dir", "test_run_dir/reset_n_spec"))
+    val chirrtl = (new ChiselStage)
+      .emitChirrtl(new ExampleModuleNeedsResetInverted, Array("--target-dir", "test_run_dir/reset_n_spec"))
     chirrtl should include("input reset :")
     (chirrtl should not).include("input reset_n :")
     (chirrtl should not).include("node reset = not(reset_n)")