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small clarifications + cleanup [skip ci]

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abejgonzalez
2019-09-20 12:22:39 -07:00
parent 37b934236a
commit edaf99ca9a
9 changed files with 36 additions and 59 deletions
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13
docs/Advanced-Usage/DTM-Debugging.rst
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@@ -3,7 +3,7 @@ Debugging with DTM/JTAG
By default, Chipyard is not setup to use the Debug Test Module (DTM) to bringup the core.
Instead, Chipyard uses TSI commands to bringup the core (which normally results in a faster simulation).
TSI simulations use the SimSerial interface to directly write the test binary into memory, while the DTM
TSI simulations use the SimSerial interface to directly write the test binary into memory, while the DTM
executes a small loop of code to write the test binary byte-wise into memory.
However, if you want to use JTAG, you must do the following steps to setup a DTM enabled system.
@@ -13,13 +13,10 @@ Creating a DTM/JTAG Config
First, a DTM config must be created for the system that you want to create.
This involves specifying the SoC top-level to add a DTM as well as configuring that DTM to use JTAG.
.. code-block:: scala
class DTMBoomConfig extends Config(
new WithDTMTop ++
new WithBootROM ++
new WithJtagDTM ++
new boom.common.SmallBoomConfig)
.. literalinclude:: ../../generators/example/src/main/scala/RocketConfigs.scala
:language: scala
:start-after: DOC include start: JtagRocket
:end-before: DOC include end: JtagRocket
In this example, the ``WithDTMTop`` mixin specifies that the top-level SoC will instantiate a DTM.
The ``WithJtagDTM`` will configure that instantiated DTM to use JTAG as the bringup method (note: this can be removed if you want a DTM-only bringup).

5
docs/Advanced-Usage/Resources.rst
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@@ -1,8 +1,9 @@
Accessing Scala Resources
===============================
A simple way to copy over a source file to the build directory to be used for a simulation compile or VLSI flow is to use the ``addResource`` functions given by FIRRTL.
It can be used in the following way:
A simple way to copy over a source file to the build directory to be used for a simulation compile or VLSI flow is to use the ``addResource`` function given by FIRRTL.
An example of its use can be seen in `generators/testchipip/src/main/scala/SerialAdapter.scala <https://github.com/ucb-bar/testchipip/blob/master/src/main/scala/SerialAdapter.scala>`_.
Here is the example inlined:
.. code-block:: scala