From 6145b1df4062e4cabe56fc55be71510f2c366cb7 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 25 Feb 2021 21:25:03 -0800 Subject: [PATCH 1/4] Use "tile" instead of "core" to assign freq's --- generators/chipyard/src/main/scala/ConfigFragments.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index 667e5148..3f18604f 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -193,7 +193,7 @@ class WithTLBackingMemory extends Config((site, here, up) => { case ExtTLMem => up(ExtMem, site) // enable TL backing memory }) -class WithTileFrequency(fMHz: Double) extends ClockNameContainsAssignment("core", fMHz) +class WithTileFrequency(fMHz: Double) extends ClockNameContainsAssignment("tile", fMHz) class WithPeripheryBusFrequencyAsDefault extends Config((site, here, up) => { case DefaultClockFrequencyKey => (site(PeripheryBusKey).dtsFrequency.get / (1000 * 1000)).toDouble From 1e2f778a6705033d67ccbcc932e66083e4646f15 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 25 Feb 2021 23:00:39 -0800 Subject: [PATCH 2/4] Bump gemmini for config changes --- generators/chipyard/src/main/scala/ConfigFragments.scala | 7 ++++--- generators/gemmini | 2 +- toolchains/esp-tools/riscv-isa-sim | 2 +- 3 files changed, 6 insertions(+), 5 deletions(-) diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index 667e5148..a861f249 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -20,7 +20,7 @@ import testchipip._ import tracegen.{TraceGenSystem} import hwacha.{Hwacha} -import gemmini.{Gemmini, GemminiConfigs} +import gemmini._ import boom.common.{BoomTileAttachParams} import cva6.{CVA6TileAttachParams} @@ -108,11 +108,12 @@ class WithMultiRoCCHwacha(harts: Int*) extends Config( }) ) -class WithMultiRoCCGemmini(harts: Int*) extends Config((site, here, up) => { +class WithMultiRoCCGemmini[T <: Data : Arithmetic, U <: Data, V <: Data]( + harts: Int*)(gemminiConfig: GemminiArrayConfig[T,U,V] = GemminiConfigs.defaultConfig) extends Config((site, here, up) => { case MultiRoCCKey => up(MultiRoCCKey, site) ++ harts.distinct.map { i => (i -> Seq((p: Parameters) => { implicit val q = p - val gemmini = LazyModule(new Gemmini(OpcodeSet.custom3, GemminiConfigs.defaultConfig)) + val gemmini = LazyModule(new Gemmini(gemminiConfig)) gemmini })) } diff --git a/generators/gemmini b/generators/gemmini index 1a6ed243..9a92fa07 160000 --- a/generators/gemmini +++ b/generators/gemmini @@ -1 +1 @@ -Subproject commit 1a6ed243874c8306e747d0f80b7773d3e2e1a3cc +Subproject commit 9a92fa07e7432376331e5f013cc00695d6ac783a diff --git a/toolchains/esp-tools/riscv-isa-sim b/toolchains/esp-tools/riscv-isa-sim index a4ed25a9..cd7d15b8 160000 --- a/toolchains/esp-tools/riscv-isa-sim +++ b/toolchains/esp-tools/riscv-isa-sim @@ -1 +1 @@ -Subproject commit a4ed25a96fdb47642b39d893b7e1ca36d07700aa +Subproject commit cd7d15b889844f730fa8e6d5688555ec584f876d From e205460986140d5ba02dacb7c58e842a84d8b035 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 26 Feb 2021 17:00:40 -0800 Subject: [PATCH 3/4] Bump esp-isa-sim --- toolchains/esp-tools/riscv-isa-sim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/toolchains/esp-tools/riscv-isa-sim b/toolchains/esp-tools/riscv-isa-sim index cd7d15b8..86265d02 160000 --- a/toolchains/esp-tools/riscv-isa-sim +++ b/toolchains/esp-tools/riscv-isa-sim @@ -1 +1 @@ -Subproject commit cd7d15b889844f730fa8e6d5688555ec584f876d +Subproject commit 86265d02e8abea3b367114393d6b0661fd35b156 From ffcb3156c9a826b64968998012c25258b351ef2f Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 1 Mar 2021 00:14:15 -0800 Subject: [PATCH 4/4] Add WithMultiRoCCFromBuildRoCC to make heterogeneous accelerator configs easier --- .../chipyard/src/main/scala/ConfigFragments.scala | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index 667e5148..465a5188 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -83,6 +83,17 @@ class WithMultiRoCC extends Config((site, here, up) => { case BuildRoCC => site(MultiRoCCKey).getOrElse(site(TileKey).hartId, Nil) }) +/** + * Assigns what was previously in the BuildRoCC key to specific harts with MultiRoCCKey + * Must be paired with WithMultiRoCC + */ +class WithMultiRoCCFromBuildRoCC(harts: Int*) extends Config((site, here, up) => { + case BuildRoCC => Nil + case MultiRoCCKey => up(MultiRoCCKey, site) ++ harts.distinct.map { i => + (i -> up(BuildRoCC, site)) + } +}) + /** * Config fragment to add Hwachas to cores based on hart *