add test case for we bug

2019-11-05 21:29:57 -08:00
parent 34984802b2
commit ecc52b9b7c
2 changed files with 94 additions and 0 deletions
--- a/macros/src/test/resources/lib-WriteEnableTest.json
+++ b/macros/src/test/resources/lib-WriteEnableTest.json
@@ -0,0 +1,24 @@
+[
+  {
+    "type" : "sram",
+    "name" : "fake_mem",
+    "width" : 64,
+    "depth" : "4096",
+    "mux" : 4,
+    "family" : "1rw",
+    "ports" : [ {
+        "address port name" : "addr",
+        "address port polarity" : "active high",
+        "clock port name" : "clk",
+        "clock port polarity" : "positive edge",
+        "write enable port name" : "wen",
+        "write enable port polarity" : "active high",
+        "read enable port name" : "ren",
+        "read enable port polarity" : "active high",
+        "output port name" : "dataout",
+        "output port polarity" : "active high",
+        "input port name" : "datain",
+        "input port polarity" : "active high"
+    } ]
+  }
+]