Merge remote-tracking branch 'origin/dev' into rc-retile

This commit is contained in:
Jerry Zhao
2020-06-23 17:00:01 +00:00
2 changed files with 27 additions and 3 deletions

View File

@@ -10,7 +10,7 @@ import chisel3.internal.sourceinfo.{SourceInfo}
import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.config.{Field, Parameters}
import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp} import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp, ExportDebug}
import freechips.rocketchip.diplomacy._ import freechips.rocketchip.diplomacy._
import freechips.rocketchip.diplomaticobjectmodel.model.{OMInterrupt} import freechips.rocketchip.diplomaticobjectmodel.model.{OMInterrupt}
import freechips.rocketchip.diplomaticobjectmodel.logicaltree.{RocketTileLogicalTreeNode, LogicalModuleTree} import freechips.rocketchip.diplomaticobjectmodel.logicaltree.{RocketTileLogicalTreeNode, LogicalModuleTree}
@@ -24,10 +24,33 @@ import freechips.rocketchip.amba.axi4._
import boom.common.{BoomTile} import boom.common.{BoomTile}
import testchipip.{DromajoHelper} import testchipip.{DromajoHelper, CanHavePeripherySerial, SerialKey}
trait CanHaveHTIF { this: BaseSubsystem =>
// Advertise HTIF if system can communicate with fesvr
if (this match {
case _: CanHavePeripherySerial if p(SerialKey) => true
case _: HasPeripheryDebug if p(ExportDebug).protocols.nonEmpty => true
case _ => false
}) {
ResourceBinding {
val htif = new Device {
def describe(resources: ResourceBindings): Description = {
val compat = resources("compat").map(_.value)
Description("htif", Map(
"compatible" -> compat))
}
}
Resource(htif, "compat").bind(ResourceString("ucb,htif0"))
}
}
}
class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem
with HasTiles with HasTiles
with CanHaveHTIF
{ {
def coreMonitorBundles = tiles.map { def coreMonitorBundles = tiles.map {
case r: RocketTile => r.module.core.rocketImpl.coreMonitorBundle case r: RocketTile => r.module.core.rocketImpl.coreMonitorBundle
@@ -36,6 +59,7 @@ class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem
override lazy val module = new ChipyardSubsystemModuleImp(this) override lazy val module = new ChipyardSubsystemModuleImp(this)
} }
class ChipyardSubsystemModuleImp[+L <: ChipyardSubsystem](_outer: L) extends BaseSubsystemModuleImp(_outer) class ChipyardSubsystemModuleImp[+L <: ChipyardSubsystem](_outer: L) extends BaseSubsystemModuleImp(_outer)
with HasResetVectorWire with HasResetVectorWire
with HasTilesModuleImp with HasTilesModuleImp

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@@ -1,6 +1,6 @@
#!/usr/bin/env bash #!/usr/bin/env bash
# Sets up FireSim for use as a library within REBAR # Sets up FireSim for use as a library within Chipyard
set -e set -e
set -o pipefail set -o pipefail