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Add Blackwell tensor core support to Chipyard
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- Update RadianceConfigs.scala with Blackwell configurations
- Update Verilator Makefile with optimized build flags
- Update submodules: radiance (Blackwell implementation), gemmini (params update)
- Update build flags and gitignore
This commit is contained in:
abnerhexu
2026-05-06 14:52:08 +08:00
parent f8c98496f5
commit ec349a854f
8 changed files with 24 additions and 10 deletions
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2
sims/common-sim-flags.mk
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@@ -1,7 +1,7 @@
#----------------------------------------------------------------------------------------
# common gcc configuration/optimization
#----------------------------------------------------------------------------------------
SIM_OPT_CXXFLAGS := -O3
SIM_OPT_CXXFLAGS := -O0
LRISCV=-lriscv
export USE_CHISEL6=1