Add PortAPI between IO and Harness blocks

generators/chipyard/src/main/scala/iobinders/Ports.scala

@@ -0,0 +1,94 @@
+package chipyard.iobinders
+
+import chisel3._
+import chisel3.experimental.{Analog}
+import sifive.blocks.devices.uart.{UARTPortIO}
+import sifive.blocks.devices.spi.{SPIFlashParams, SPIPortIO}
+import sifive.blocks.devices.i2c.{I2CPort}
+import sifive.blocks.devices.gpio.{GPIOPortIO}
+import testchipip._
+import icenet.{NICIOvonly, NICConfig}
+import org.chipsalliance.cde.config.{Parameters}
+import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4EdgeParameters}
+import freechips.rocketchip.subsystem.{MemoryPortParams, MasterPortParams, SlavePortParams}
+import freechips.rocketchip.devices.debug.{ClockedDMIIO}
+import freechips.rocketchip.util.{HeterogeneousBag}
+import freechips.rocketchip.tilelink.{TLBundle}
+
+trait Port[T <: Data] {
+  val io: T
+}
+
+// These case classes are generated by IOBinders, and interpreted by HarnessBinders
+case class GPIOPort        (val io: Analog, val gpioId: Int, val pinId: Int)
+    extends Port[Analog]
+
+case class GPIOPinsPort    (val io: GPIOPortIO, val gpioId: Int)
+    extends Port[GPIOPortIO]
+
+case class I2CPort         (val io: sifive.blocks.devices.i2c.I2CPort)
+    extends Port[sifive.blocks.devices.i2c.I2CPort]
+
+case class UARTPort        (val io: UARTPortIO, val uartNo: Int, val freqMHz: Int)
+    extends Port[UARTPortIO]
+
+case class SPIFlashPort    (val io: SPIChipIO, val params: SPIFlashParams, val spiId: Int)
+    extends Port[SPIChipIO]
+
+case class SPIPort         (val io: SPIPortIO)
+    extends Port[SPIPortIO]
+
+case class BlockDevicePort (val io: ClockedIO[BlockDeviceIO], val params: BlockDeviceConfig)
+    extends Port[ClockedIO[BlockDeviceIO]]
+
+case class NICPort         (val io: ClockedIO[NICIOvonly], val params: NICConfig)
+    extends Port[ClockedIO[NICIOvonly]]
+
+case class AXI4MemPort     (val io: ClockedIO[AXI4Bundle], val params: MemoryPortParams, val edge: AXI4EdgeParameters, val clockFreqMHz: Int)
+    extends Port[ClockedIO[AXI4Bundle]]
+
+case class AXI4MMIOPort    (val io: ClockedIO[AXI4Bundle], val params: MasterPortParams, val edge: AXI4EdgeParameters)
+    extends Port[ClockedIO[AXI4Bundle]]
+
+case class AXI4InPort      (val io: ClockedIO[AXI4Bundle], val params: SlavePortParams)
+    extends Port[ClockedIO[AXI4Bundle]]
+
+case class ExtIntPort      (val io: UInt)
+    extends Port[UInt]
+
+case class DMIPort         (val io: ClockedDMIIO)
+    extends Port[ClockedDMIIO]
+
+case class JTAGPort        (val io: JTAGChipIO)
+    extends Port[JTAGChipIO]
+
+case class SerialTLPort    (val io: ClockedIO[SerialIO], val params: SerialTLParams, val serdesser: TLSerdesser, val portId: Int)
+    extends Port[ClockedIO[SerialIO]]
+
+case class UARTTSIPort     (val io: UARTTSIIO)
+    extends Port[UARTTSIIO]
+
+case class SuccessPort     (val io: Bool)
+    extends Port[Bool]
+
+case class TracePort       (val io: TraceOutputTop, val cosimCfg: SpikeCosimConfig)
+    extends Port[TraceOutputTop]
+
+case class CustomBootPort  (val io: Bool)
+    extends Port[Bool]
+
+case class ClockPort       (val io: Clock, val freqMHz: Double)
+    extends Port[Clock]
+
+case class ResetPort       (val io: AsyncReset)
+    extends Port[Reset]
+
+case class DebugResetPort  (val io: Reset)
+    extends Port[Reset]
+
+case class JTAGResetPort   (val io: Reset)
+    extends Port[Reset]
+
+case class TLMemPort       (val io: HeterogeneousBag[TLBundle])
+    extends Port[HeterogeneousBag[TLBundle]]
+