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Add PortAPI between IO and Harness blocks

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This commit is contained in:
Jerry Zhao
2023-10-02 17:30:13 -07:00
parent 8c1319073c
commit eb3a0aecf4
32 changed files with 715 additions and 822 deletions
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25
fpga/src/main/scala/vcu118/bringup/IOBinders.scala
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@@ -11,27 +11,10 @@ import sifive.blocks.devices.i2c.{HasPeripheryI2CModuleImp}
import testchipip.{HasPeripheryTSIHostWidget, TSIHostWidgetIO}
import chipyard.iobinders.{OverrideIOBinder}
import chipyard.iobinders.{OverrideIOBinder, Port, TLMemPort}
class WithGPIOIOPassthrough extends OverrideIOBinder({
(system: HasPeripheryGPIOModuleImp) => {
val io_gpio_pins_temp = system.gpio.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"gpio_$i") }
(io_gpio_pins_temp zip system.gpio).map { case (io, sysio) =>
io <> sysio
}
(io_gpio_pins_temp, Nil)
}
})
class WithI2CIOPassthrough extends OverrideIOBinder({
(system: HasPeripheryI2CModuleImp) => {
val io_i2c_pins_temp = system.i2c.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"i2c_$i") }
(io_i2c_pins_temp zip system.i2c).map { case (io, sysio) =>
io <> sysio
}
(io_i2c_pins_temp, Nil)
}
})
case class TSIHostWidgetPort(val io: TSIHostWidgetIO)
extends Port[TSIHostWidgetIO]
class WithTSITLIOPassthrough extends OverrideIOBinder({
(system: HasPeripheryTSIHostWidget) => {
@@ -42,6 +25,6 @@ class WithTSITLIOPassthrough extends OverrideIOBinder({
require(system.tsiSerial.size == 1)
val io_tsi_serial_pins_temp = IO(DataMirror.internal.chiselTypeClone[TSIHostWidgetIO](system.tsiSerial.head)).suggestName("tsi_serial")
io_tsi_serial_pins_temp <> system.tsiSerial.head
(Seq(io_tsi_tl_mem_pins_temp, io_tsi_serial_pins_temp), Nil)
(Seq(TLMemPort(io_tsi_tl_mem_pins_temp), TSIHostWidgetPort(io_tsi_serial_pins_temp)), Nil)
}
})