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Add PortAPI between IO and Harness blocks

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This commit is contained in:
Jerry Zhao
2023-10-02 17:30:13 -07:00
parent 8c1319073c
commit eb3a0aecf4
32 changed files with 715 additions and 822 deletions
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4
fpga/src/main/scala/vcu118/bringup/Configs.scala
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@@ -20,6 +20,7 @@ import testchipip.{PeripheryTSIHostKey, TSIHostParams, TSIHostSerdesParams}
import chipyard.{BuildSystem}
import chipyard.fpga.vcu118.{WithVCU118Tweaks, WithFPGAFrequency, VCU118DDR2Size}
import chipyard.iobinders.{WithGPIOPunchthrough}
class WithBringupPeripherals extends Config((site, here, up) => {
case PeripheryUARTKey => up(PeripheryUARTKey, site) ++ List(UARTParams(address = BigInt(0x64003000L)))
@@ -80,8 +81,7 @@ class WithBringupAdditions extends Config(
new WithBringupGPIO ++
new WithBringupTSIHost ++
new WithTSITLIOPassthrough ++
new WithI2CIOPassthrough ++
new WithGPIOIOPassthrough ++
new WithGPIOPunchthrough ++
new WithBringupPeripherals ++
new WithBringupVCU118System)