Add PortAPI between IO and Harness blocks

2023-10-02 17:30:13 -07:00
parent 8c1319073c
commit eb3a0aecf4
32 changed files with 715 additions and 822 deletions
--- a/fpga/src/main/scala/vc707/Configs.scala
+++ b/fpga/src/main/scala/vc707/Configs.scala
@@ -53,10 +53,6 @@ class WithVC707Tweaks extends Config (
  new WithVC707UARTHarnessBinder ++
  new WithVC707SPISDCardHarnessBinder ++
  new WithVC707DDRMemHarnessBinder ++
-  // io binders
-  new WithUARTIOPassthrough ++
-  new WithSPIIOPassthrough ++
-  new WithTLIOPassthrough ++
  // other configuration
  new WithDefaultPeripherals ++
  new chipyard.config.WithTLBackingMemory ++ // use TL backing memory