diff --git a/.gitmodules b/.gitmodules index 3d3a7a73..73e556a4 100644 --- a/.gitmodules +++ b/.gitmodules @@ -25,3 +25,6 @@ [submodule "generators/boom"] path = generators/boom url = git@github.com:riscv-boom/riscv-boom.git +[submodule "generators/sifive-blocks"] + path = generators/sifive-blocks + url = git@github.com:sifive/sifive-blocks.git diff --git a/build.sbt b/build.sbt index 41ccfc36..0f379698 100644 --- a/build.sbt +++ b/build.sbt @@ -42,6 +42,7 @@ def conditionalDependsOn(prj: Project): Project = { } lazy val example = conditionalDependsOn(project in file(".")) + .dependsOn(boom) .settings(commonSettings) lazy val boom = (project in file("generators/boom")) diff --git a/generators/sifive-blocks b/generators/sifive-blocks new file mode 160000 index 00000000..24dd5378 --- /dev/null +++ b/generators/sifive-blocks @@ -0,0 +1 @@ +Subproject commit 24dd537894379dc160ed9e15d33444439822ab5b diff --git a/src/main/scala/boomexample/Configs.scala b/src/main/scala/boomexample/Configs.scala new file mode 100644 index 00000000..738e2922 --- /dev/null +++ b/src/main/scala/boomexample/Configs.scala @@ -0,0 +1,90 @@ +package boomexample + +import chisel3._ +import freechips.rocketchip.config.{Parameters, Config} +import freechips.rocketchip.subsystem.{WithRoccExample, WithNMemoryChannels} +import freechips.rocketchip.diplomacy.{LazyModule, ValName} +import freechips.rocketchip.devices.tilelink.BootROMParams +import freechips.rocketchip.tile.XLen +import testchipip._ + +class WithBootROM extends Config((site, here, up) => { + case BootROMParams => BootROMParams( + contentFileName = s"./bootrom/bootrom.rv${site(XLen)}.img") +}) + +object ConfigValName { + implicit val valName = ValName("TestHarness") +} +import ConfigValName._ + +class WithBoomExampleTop extends Config((site, here, up) => { + case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => { + Module(LazyModule(new BoomExampleTop()(p)).module) + } +}) + +class WithPWM extends Config((site, here, up) => { + case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => + Module(LazyModule(new BoomExampleTopWithPWMTL()(p)).module) +}) + +class WithPWMAXI4 extends Config((site, here, up) => { + case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => + Module(LazyModule(new BoomExampleTopWithPWMAXI4()(p)).module) +}) + +class WithBlockDeviceModel extends Config((site, here, up) => { + case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => { + val top = Module(LazyModule(new BoomExampleTopWithBlockDevice()(p)).module) + top.connectBlockDeviceModel() + top + } +}) + +class WithSimBlockDevice extends Config((site, here, up) => { + case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => { + val top = Module(LazyModule(new BoomExampleTopWithBlockDevice()(p)).module) + top.connectSimBlockDevice(clock, reset) + top + } +}) + +class BaseBoomExampleConfig extends Config( + new WithBootROM ++ + new boom.system.SmallBoomConfig) + +class DefaultBoomExampleConfig extends Config( + new WithBoomExampleTop ++ + new BaseBoomExampleConfig) + +class RoccBoomExampleConfig extends Config( + new WithRoccExample ++ + new DefaultBoomExampleConfig) + +class PWMBoomExampleConfig extends Config( + new WithPWM ++ + new BaseBoomExampleConfig) + +class PWMAXI4BoomExampleConfig extends Config( + new WithPWMAXI4 ++ + new BaseBoomExampleConfig) + +class SimBlockDeviceBoomExampleConfig extends Config( + new WithBlockDevice ++ + new WithSimBlockDevice ++ + new BaseBoomExampleConfig) + +class BlockDeviceModelBoomExampleConfig extends Config( + new WithBlockDevice ++ + new WithBlockDeviceModel ++ + new BaseBoomExampleConfig) + +class DualCoreBoomExampleConfig extends Config( + // Core gets tacked onto existing list + new boom.system.WithNBoomCores(2) ++ + new DefaultBoomExampleConfig) + +class RV32BoomExampleConfig extends Config( + new WithBootROM ++ + new boom.system.SmallRV32UnifiedBoomConfig) diff --git a/src/main/scala/boomexample/TestHarness.scala b/src/main/scala/boomexample/TestHarness.scala new file mode 100644 index 00000000..fd5e766d --- /dev/null +++ b/src/main/scala/boomexample/TestHarness.scala @@ -0,0 +1,44 @@ +package boomexample + +import chisel3._ +import chisel3.experimental._ +import firrtl.transforms.{BlackBoxResourceAnno, BlackBoxSourceHelper} +import freechips.rocketchip.diplomacy.LazyModule +import freechips.rocketchip.config.{Field, Parameters} +import freechips.rocketchip.util.GeneratorApp + +case object BuildTop extends Field[(Clock, Bool, Parameters) => BoomExampleTopModule[BoomExampleTop]] + +class TestHarness(implicit val p: Parameters) extends Module { + val io = IO(new Bundle { + val success = Output(Bool()) + }) + + val dut = p(BuildTop)(clock, reset.toBool, p) + dut.debug := DontCare + dut.connectSimAXIMem() + dut.connectSimAXIMMIO() + dut.dontTouchPorts() + dut.tieOffInterrupts() + dut.l2_frontend_bus_axi4.foreach(axi => { + axi.tieoff() + experimental.DataMirror.directionOf(axi.ar.ready) match { + case core.ActualDirection.Input => + axi.r.bits := DontCare + axi.b.bits := DontCare + case core.ActualDirection.Output => + axi.aw.bits := DontCare + axi.ar.bits := DontCare + axi.w.bits := DontCare + } + }) + io.success := dut.connectSimSerial() +} + +object Generator extends GeneratorApp { + val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs + generateFirrtl + generateAnno + generateTestSuiteMakefrags + generateArtefacts +} diff --git a/src/main/scala/boomexample/Top.scala b/src/main/scala/boomexample/Top.scala new file mode 100644 index 00000000..312d43fd --- /dev/null +++ b/src/main/scala/boomexample/Top.scala @@ -0,0 +1,54 @@ +package boomexample + +import chisel3._ +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.system._ +import freechips.rocketchip.config.Parameters +import freechips.rocketchip.devices.tilelink._ +import freechips.rocketchip.util.DontTouch +import testchipip._ +import example.{HasPeripheryPWMTL, HasPeripheryPWMAXI4, HasPeripheryPWMTLModuleImp, HasPeripheryPWMAXI4ModuleImp} + +//--------------------------------------------------------------------------------------------------------- + +class BoomExampleTop(implicit p: Parameters) extends boom.system.ExampleBoomSystem + with HasNoDebug + with HasPeripherySerial { + override lazy val module = new BoomExampleTopModule(this) +} + +class BoomExampleTopModule[+L <: BoomExampleTop](l: L) extends boom.system.ExampleBoomSystemModule(l) + with HasRTCModuleImp + with HasNoDebugModuleImp + with HasPeripherySerialModuleImp + with DontTouch + +//--------------------------------------------------------------------------------------------------------- + +class BoomExampleTopWithPWMTL(implicit p: Parameters) extends BoomExampleTop + with HasPeripheryPWMTL { + override lazy val module = new BoomExampleTopWithPWMTLModule(this) +} + +class BoomExampleTopWithPWMTLModule(l: BoomExampleTopWithPWMTL) extends BoomExampleTopModule(l) + with HasPeripheryPWMTLModuleImp + +//--------------------------------------------------------------------------------------------------------- + +class BoomExampleTopWithPWMAXI4(implicit p: Parameters) extends BoomExampleTop + with HasPeripheryPWMAXI4 { + override lazy val module = new BoomExampleTopWithPWMAXI4Module(this) +} + +class BoomExampleTopWithPWMAXI4Module(l: BoomExampleTopWithPWMAXI4) extends BoomExampleTopModule(l) + with HasPeripheryPWMAXI4ModuleImp + +//--------------------------------------------------------------------------------------------------------- + +class BoomExampleTopWithBlockDevice(implicit p: Parameters) extends BoomExampleTop + with HasPeripheryBlockDevice { + override lazy val module = new BoomExampleTopWithBlockDeviceModule(this) +} + +class BoomExampleTopWithBlockDeviceModule(l: BoomExampleTopWithBlockDevice) extends BoomExampleTopModule(l) + with HasPeripheryBlockDeviceModuleImp diff --git a/src/main/scala/example/Top.scala b/src/main/scala/example/Top.scala index bcc745ad..bb156575 100644 --- a/src/main/scala/example/Top.scala +++ b/src/main/scala/example/Top.scala @@ -8,6 +8,8 @@ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.util.DontTouch import testchipip._ +//--------------------------------------------------------------------------------------------------------- + class ExampleTop(implicit p: Parameters) extends ExampleRocketSystem //RocketSubsystem with CanHaveMasterAXI4MemPort with HasPeripheryBootROM @@ -27,6 +29,8 @@ class ExampleTopModule[+L <: ExampleTop](l: L) extends ExampleRocketSystemModule with HasPeripherySerialModuleImp with DontTouch +//--------------------------------------------------------------------------------------------------------- + class ExampleTopWithPWMTL(implicit p: Parameters) extends ExampleTop with HasPeripheryPWMTL { override lazy val module = new ExampleTopWithPWMTLModule(this) @@ -35,6 +39,8 @@ class ExampleTopWithPWMTL(implicit p: Parameters) extends ExampleTop class ExampleTopWithPWMTLModule(l: ExampleTopWithPWMTL) extends ExampleTopModule(l) with HasPeripheryPWMTLModuleImp +//--------------------------------------------------------------------------------------------------------- + class ExampleTopWithPWMAXI4(implicit p: Parameters) extends ExampleTop with HasPeripheryPWMAXI4 { override lazy val module = new ExampleTopWithPWMAXI4Module(this) @@ -43,6 +49,8 @@ class ExampleTopWithPWMAXI4(implicit p: Parameters) extends ExampleTop class ExampleTopWithPWMAXI4Module(l: ExampleTopWithPWMAXI4) extends ExampleTopModule(l) with HasPeripheryPWMAXI4ModuleImp +//--------------------------------------------------------------------------------------------------------- + class ExampleTopWithBlockDevice(implicit p: Parameters) extends ExampleTop with HasPeripheryBlockDevice { override lazy val module = new ExampleTopWithBlockDeviceModule(this)