From e98ebec30dceec690e13cbb27ee28e217558016f Mon Sep 17 00:00:00 2001
From: KlepD-SAL <61977269+KlepD-SAL@users.noreply.github.com>
Date: Mon, 20 Apr 2020 20:47:59 +0200
Subject: [PATCH] Added note about resource usage during elaboration to docs
 (#517)

On computers with limited resources (like main memory) the elaboration will fail with the message 'make: *** [firrtl_temp] Error 137'. Since no further explaination of the error is given, its meaning should be mentioned in the docs.
---
 docs/Simulation/Software-RTL-Simulation.rst | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/docs/Simulation/Software-RTL-Simulation.rst b/docs/Simulation/Software-RTL-Simulation.rst
index 957913e9..bdafd60f 100644
--- a/docs/Simulation/Software-RTL-Simulation.rst
+++ b/docs/Simulation/Software-RTL-Simulation.rst
@@ -49,6 +49,8 @@ Simulating The Default Example
 To compile the example design, run ``make`` in the selected verilator or VCS directory.
 This will elaborate the ``RocketConfig`` in the example project.
 
+.. Note:: The elaboration of ``RocketConfig`` requires about 6.5 GB of main memory. Otherwise the process will fail with ``make: *** [firrtl_temp] Error 137`` which is most likely related to limited resources. Other configurations might require even more main memory.
+
 An executable called ``simulator-chipyard-RocketConfig`` will be produced.
 This executable is a simulator that has been compiled based on the design that was built.
 You can then use this executable to run any compatible RV64 code.