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Fix Arty FPGA reset harness binder

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This commit is contained in:
Jerry Zhao
2023-04-01 13:53:56 -07:00
parent 3e4c141b4e
commit e93bc3bed7
2 changed files with 6 additions and 6 deletions
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10
fpga/src/main/scala/arty/HarnessBinders.scala
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@@ -15,15 +15,15 @@ import chipyard.harness.{ComposeHarnessBinder, OverrideHarnessBinder}
import chipyard.iobinders.JTAGChipIO
class WithArtyResetHarnessBinder extends ComposeHarnessBinder({
(system: HasPeripheryDebug, th: ArtyFPGATestHarness, ports: Seq[Bool]) => {
require(ports.size == 2)
(system: HasPeripheryDebug, th: ArtyFPGATestHarness, ports: Seq[Data]) => {
val resetPorts = ports.collect { case b: Bool => b }
require(resetPorts.size == 2)
withClockAndReset(th.clock_32MHz, th.ck_rst) {
// Debug module reset
th.dut_ndreset := ports(0)
th.dut_ndreset := resetPorts(0)
// JTAG reset
ports(1) := PowerOnResetFPGAOnly(th.clock_32MHz)
resetPorts(1) := PowerOnResetFPGAOnly(th.clock_32MHz)
}
}
})