From e93bc3bed7f6521eea49e3906001e25f53eca168 Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Sat, 1 Apr 2023 13:53:56 -0700
Subject: [PATCH] Fix Arty FPGA reset harness binder

---
 fpga/src/main/scala/arty/Configs.scala        |  2 +-
 fpga/src/main/scala/arty/HarnessBinders.scala | 10 +++++-----
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/fpga/src/main/scala/arty/Configs.scala b/fpga/src/main/scala/arty/Configs.scala
index 421ba355..10af0223 100644
--- a/fpga/src/main/scala/arty/Configs.scala
+++ b/fpga/src/main/scala/arty/Configs.scala
@@ -17,9 +17,9 @@ import chipyard.{BuildSystem}
 
 // DOC include start: AbstractArty and Rocket
 class WithArtyTweaks extends Config(
+  new WithArtyResetHarnessBinder ++
   new WithArtyJTAGHarnessBinder ++
   new WithArtyUARTHarnessBinder ++
-  new WithArtyResetHarnessBinder ++
   new WithDebugResetPassthrough ++
 
   new chipyard.config.WithDTSTimebase(32768) ++
diff --git a/fpga/src/main/scala/arty/HarnessBinders.scala b/fpga/src/main/scala/arty/HarnessBinders.scala
index 720fafca..84d47967 100644
--- a/fpga/src/main/scala/arty/HarnessBinders.scala
+++ b/fpga/src/main/scala/arty/HarnessBinders.scala
@@ -15,15 +15,15 @@ import chipyard.harness.{ComposeHarnessBinder, OverrideHarnessBinder}
 import chipyard.iobinders.JTAGChipIO
 
 class WithArtyResetHarnessBinder extends ComposeHarnessBinder({
-  (system: HasPeripheryDebug, th: ArtyFPGATestHarness, ports: Seq[Bool]) => {
-    require(ports.size == 2)
-
+  (system: HasPeripheryDebug, th: ArtyFPGATestHarness, ports: Seq[Data]) => {
+    val resetPorts = ports.collect { case b: Bool => b }
+    require(resetPorts.size == 2)
     withClockAndReset(th.clock_32MHz, th.ck_rst) {
       // Debug module reset
-      th.dut_ndreset := ports(0)
+      th.dut_ndreset := resetPorts(0)
 
       // JTAG reset
-      ports(1) := PowerOnResetFPGAOnly(th.clock_32MHz)
+      resetPorts(1) := PowerOnResetFPGAOnly(th.clock_32MHz)
     }
   }
 })