From e8e0f3e9022802a024f2b4698b6ed9937d2b421b Mon Sep 17 00:00:00 2001 From: joey0320 Date: Sat, 31 Dec 2022 21:50:56 -0800 Subject: [PATCH] Fix HARNESS_* to MODEL_* for consistence --- common.mk | 31 +++++++++++++++++++------------ docs/VLSI/Basic-Flow.rst | 2 +- variables.mk | 6 +++--- vlsi/Makefile | 14 +++++++------- 4 files changed, 30 insertions(+), 23 deletions(-) diff --git a/common.mk b/common.mk index 161f4bc0..fbe92737 100644 --- a/common.mk +++ b/common.mk @@ -137,7 +137,7 @@ firrtl: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) ######################################################################################### # create verilog files rules and variables ######################################################################################### -FIRTOOL_TARGETS = \ +SFC_FIRTOOL_TARGETS = \ $(FIRTOOL_SMEMS_CONF) \ $(FIRTOOL_TOP_SMEMS_JSON) \ $(FIRTOOL_TOP_HRCHY_JSON) \ @@ -150,10 +150,17 @@ SFC_REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SFC_SMEMS_CONF) # DOC include start: FirrtlCompiler +# This step can take either one of two paths. The first path is when SFC +# compiles Chisel to CHIRRTL, and FIRTOOL compiles CHIRRTL to Verilog. Otherwise, +# when custom FIRRTL transforms are included or if a Fixed type is used within +# the dut, SFC compiles Chisel to LowFIRRTL and FIRTOOL compiles it to Verilog. +# Users can indicate to the Makefile of custom FIRRTL transforms by setting the +# "ENABLE_CUSTOM_FIRRTL_PASS" env variable. +# # hack: lower to low firrtl if Fixed types are found # hack: when using dontTouch, io.cpu annotations are not removed by SFC, # hence we remove them manually by using jq before passing them to firtool -$(FIRTOOL_TARGETS) &: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(VLOG_SOURCES) +$(SFC_FIRTOOL_TARGETS) &: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(VLOG_SOURCES) ifeq (,$(ENABLE_CUSTOM_FIRRTL_PASS)) $(eval SFC_LEVEL := $(if $(shell grep "Fixed<" $(FIRRTL_FILE)), low, none)) $(eval EXTRA_FIRRTL_OPTIONS += $(if $(shell grep "Fixed<" $(FIRRTL_FILE)), $(SFC_REPL_SEQ_MEM),)) @@ -172,7 +179,7 @@ endif --allow-unrecognized-annotations \ -X $(SFC_LEVEL) \ $(EXTRA_FIRRTL_OPTIONS)) - -mv $(SFC_FIRRTL_BASENAME).lo.fir $(SFC_FIRRTL_FILE) + -mv $(SFC_FIRRTL_BASENAME).lo.fir $(SFC_FIRRTL_FILE) # Optionally change file type when SFC generates LowFIRRTL @if [ "$(SFC_LEVEL)" = low ]; then cat $(SFC_ANNO_FILE) | jq 'del(.[] | select(.target | test("io.cpu"))?)' > /tmp/unnec-anno-deleted.sfc.anno.json; fi @if [ "$(SFC_LEVEL)" = low ]; then cat /tmp/unnec-anno-deleted.sfc.anno.json > $(SFC_ANNO_FILE) && rm /tmp/unnec-anno-deleted.sfc.anno.json; fi firtool \ @@ -211,31 +218,31 @@ $(TOP_MODS_FILELIST) $(MODEL_MODS_FILELIST) $(ALL_MODS_FILELIST) $(BB_MODS_FILEL $(SED) -i 's/\.\///' $(BB_MODS_FILELIST) sort -u $(TOP_MODS_FILELIST) $(MODEL_MODS_FILELIST) $(BB_MODS_FILELIST) > $(ALL_MODS_FILELIST) -$(TOP_SMEMS_CONF) $(HARNESS_SMEMS_CONF) &: $(FIRTOOL_TOP_SMEMS_JSON) $(FIRTOOL_MODEL_SMEMS_JSON) $(FIRTOOL_SMEMS_CONF) +$(TOP_SMEMS_CONF) $(MODEL_SMEMS_CONF) &: $(FIRTOOL_SMEMS_CONF) $(FIRTOOL_MODEL_HRCHY_JSON) $(base_dir)/scripts/split-mems-conf.py \ --in-smems-conf $(FIRTOOL_SMEMS_CONF) \ --in-model-hrchy-json $(FIRTOOL_MODEL_HRCHY_JSON) \ --dut-module-name $(TOP) \ --model-module-name $(MODEL) \ --out-dut-smems-conf $(TOP_SMEMS_CONF) \ - --out-model-smems-conf $(HARNESS_SMEMS_CONF) + --out-model-smems-conf $(MODEL_SMEMS_CONF) # This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs -MACROCOMPILER_MODE ?= --mode synflops +TOP_MACROCOMPILER_MODE ?= --mode synflops $(TOP_SMEMS_FILE) $(TOP_SMEMS_FIR) &: $(TOP_SMEMS_CONF) - $(call run_scala_main,tapeout,barstools.macros.MacroCompiler,-n $(TOP_SMEMS_CONF) -v $(TOP_SMEMS_FILE) -f $(TOP_SMEMS_FIR) $(MACROCOMPILER_MODE)) + $(call run_scala_main,tapeout,barstools.macros.MacroCompiler,-n $(TOP_SMEMS_CONF) -v $(TOP_SMEMS_FILE) -f $(TOP_SMEMS_FIR) $(TOP_MACROCOMPILER_MODE)) -HARNESS_MACROCOMPILER_MODE = --mode synflops -$(HARNESS_SMEMS_FILE) $(HARNESS_SMEMS_FIR) &: $(HARNESS_SMEMS_CONF) | $(TOP_SMEMS_FILE) - $(call run_scala_main,tapeout,barstools.macros.MacroCompiler, -n $(HARNESS_SMEMS_CONF) -v $(HARNESS_SMEMS_FILE) -f $(HARNESS_SMEMS_FIR) $(HARNESS_MACROCOMPILER_MODE)) +MODEL_MACROCOMPILER_MODE = --mode synflops +$(MODEL_SMEMS_FILE) $(MODEL_SMEMS_FIR) &: $(MODEL_SMEMS_CONF) | $(TOP_SMEMS_FILE) + $(call run_scala_main,tapeout,barstools.macros.MacroCompiler, -n $(MODEL_SMEMS_CONF) -v $(MODEL_SMEMS_FILE) -f $(MODEL_SMEMS_FIR) $(MODEL_MACROCOMPILER_MODE)) ######################################################################################## # remove duplicate files and headers in list of simulation file inputs ######################################################################################## -$(sim_common_files): $(sim_files) $(ALL_MODS_FILELIST) $(TOP_SMEMS_FILE) $(HARNESS_SMEMS_FILE) +$(sim_common_files): $(sim_files) $(ALL_MODS_FILELIST) $(TOP_SMEMS_FILE) $(MODEL_SMEMS_FILE) sort -u $(sim_files) $(ALL_MODS_FILELIST) | grep -v '.*\.\(svh\|h\)$$' > $@ echo "$(TOP_SMEMS_FILE)" >> $@ - echo "$(HARNESS_SMEMS_FILE)" >> $@ + echo "$(MODEL_SMEMS_FILE)" >> $@ ######################################################################################### # helper rule to just make verilog files diff --git a/docs/VLSI/Basic-Flow.rst b/docs/VLSI/Basic-Flow.rst index 610f6958..6f7c456b 100644 --- a/docs/VLSI/Basic-Flow.rst +++ b/docs/VLSI/Basic-Flow.rst @@ -64,7 +64,7 @@ As in the rest of the Chipyard flows, we specify our SoC configuration using the However, unlike the rest of the Chipyard flows, in the case of physical design we might be interested in working in a hierarchical fashion and therefore we would like to work on a single module. Therefore, we can also specify a ``VLSI_TOP`` make variable with the same of a specific Verilog module (which should also match the name of the equivalent Chisel module) which we would like to work on. The makefile will automatically call tools such as Barstools and the MacroCompiler (:ref:`Tools/Barstools:barstools`) in order to make the generated Verilog more VLSI friendly. -By default, the MacroCompiler will attempt to map memories into the SRAM options within the Hammer technology plugin. However, if you are working with a new process technology and prefer to work with flip-flop arrays, you can configure the MacroCompiler using the ``MACROCOMPILER_MODE`` make variable. For example, if your technology plugin does not have an SRAM compiler ready, you can use the ``MACROCOMPILER_MODE='--mode synflops'`` option (Note that synthesizing a design with only flipflops is very slow and will often may not meet constraints). +By default, the MacroCompiler will attempt to map memories into the SRAM options within the Hammer technology plugin. However, if you are working with a new process technology and prefer to work with flip-flop arrays, you can configure the MacroCompiler using the ``TOP_MACROCOMPILER_MODE`` make variable. For example, if your technology plugin does not have an SRAM compiler ready, you can use the ``MACROCOMPILER_MODE='--mode synflops'`` option (Note that synthesizing a design with only flipflops is very slow and will often may not meet constraints). We call the ``make buildfile`` command while also specifying the name of the process technology we are working with (same ``tech_name`` for the configuration files and plugin name) and the configuration files we created. Note, in the ASAP7 tutorial ((:ref:`tutorial`)) these configuration files are merged into a single file called ``example-asap7.yml``. diff --git a/variables.mk b/variables.mk index a457a813..d4f035f8 100644 --- a/variables.mk +++ b/variables.mk @@ -171,9 +171,9 @@ SFC_SMEMS_CONF ?= $(build_dir)/$(long_name).sfc.mems.conf TOP_SMEMS_CONF ?= $(build_dir)/$(long_name).top.mems.conf TOP_SMEMS_FILE ?= $(OUT_DIR)/$(long_name).top.mems.v TOP_SMEMS_FIR ?= $(build_dir)/$(long_name).top.mems.fir -HARNESS_SMEMS_CONF ?= $(build_dir)/$(long_name).harness.mems.conf -HARNESS_SMEMS_FILE ?= $(OUT_DIR)/$(long_name).harness.mems.v -HARNESS_SMEMS_FIR ?= $(build_dir)/$(long_name).harness.mems.fir +MODEL_SMEMS_CONF ?= $(build_dir)/$(long_name).model.mems.conf +MODEL_SMEMS_FILE ?= $(OUT_DIR)/$(long_name).model.mems.v +MODEL_SMEMS_FIR ?= $(build_dir)/$(long_name).model.mems.fir # top module files to include TOP_MODS_FILELIST ?= $(build_dir)/$(long_name).top.f diff --git a/vlsi/Makefile b/vlsi/Makefile index 0df1f7f9..228401b2 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -28,9 +28,9 @@ SMEMS_CACHE ?= $(tech_dir)/sram-cache.json SMEMS_HAMMER ?= $(build_dir)/$(long_name).mems.hammer.json ifdef USE_SRAM_COMPILER - MACROCOMPILER_MODE ?= -l $(SMEMS_COMP) --use-compiler -hir $(SMEMS_HAMMER) --mode strict + TOP_MACROCOMPILER_MODE ?= -l $(SMEMS_COMP) --use-compiler -hir $(SMEMS_HAMMER) --mode strict else - MACROCOMPILER_MODE ?= -l $(SMEMS_CACHE) -hir $(SMEMS_HAMMER) --mode strict + TOP_MACROCOMPILER_MODE ?= -l $(SMEMS_CACHE) -hir $(SMEMS_HAMMER) --mode strict endif ENV_YML ?= $(vlsi_dir)/env.yml @@ -121,12 +121,12 @@ SIM_DEBUG_CONF = $(OBJ_DIR)/sim-debug-inputs.yml SIM_TIMING_CONF = $(OBJ_DIR)/sim-timing-inputs.yml include $(vlsi_dir)/sim.mk -$(SIM_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) $(dramsim_lib) +$(SIM_CONF): $(VLSI_RTL) $(MODEL_FILE) $(MODEL_SMEMS_FILE) $(sim_common_files) $(dramsim_lib) mkdir -p $(dir $@) echo "sim.inputs:" > $@ echo " top_module: $(VLSI_TOP)" >> $@ echo " input_files:" >> $@ - for x in $(HARNESS_FILE) $(HARNESS_SMEMS_FILE); do \ + for x in $(MODEL_FILE) $(MODEL_SMEMS_FILE); do \ echo ' - "'$$x'"' >> $@; \ done echo " input_files_meta: 'append'" >> $@ @@ -163,7 +163,7 @@ ifneq ($(BINARY), ) endif echo " tb_dut: 'TestDriver.testHarness.$(VLSI_HARNESS_DUT_NAME)'" >> $@ -$(SIM_DEBUG_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) +$(SIM_DEBUG_CONF): $(VLSI_RTL) $(MODEL_FILE) $(MODEL_SMEMS_FILE) $(sim_common_files) mkdir -p $(dir $@) mkdir -p $(output_dir) echo "sim.inputs:" > $@ @@ -186,7 +186,7 @@ else echo "sim.outputs.waveforms: ['$(sim_out_name).vpd']" >> $@ endif -$(SIM_TIMING_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) +$(SIM_TIMING_CONF): $(VLSI_RTL) $(MODEL_FILE) $(MODEL_SMEMS_FILE) $(sim_common_files) mkdir -p $(dir $@) echo "sim.inputs:" > $@ echo " defines: ['NTC']" >> $@ @@ -195,7 +195,7 @@ $(SIM_TIMING_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_comm POWER_CONF = $(OBJ_DIR)/power-inputs.yml include $(vlsi_dir)/power.mk -$(POWER_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) +$(POWER_CONF): $(VLSI_RTL) $(MODEL_FILE) $(MODEL_SMEMS_FILE) $(sim_common_files) mkdir -p $(dir $@) echo "power.inputs:" > $@ echo " tb_dut: 'testHarness/$(VLSI_HARNESS_DUT_NAME)'" >> $@