From e75b107cf37b01b01f7ea1873d367dad6c1e900d Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sat, 8 Oct 2022 11:37:45 -0700 Subject: [PATCH] Reorg + Cleanup --- common.mk | 65 ++++++++------ conda-reqs/chipyard.yaml | 1 + conda-requirements-riscv-tools.yaml | 133 ++++++++++++++++++++++++++++ variables.mk | 39 +++----- 4 files changed, 185 insertions(+), 53 deletions(-) create mode 100644 conda-requirements-riscv-tools.yaml diff --git a/common.mk b/common.mk index 7ca6cbb1..87078369 100644 --- a/common.mk +++ b/common.mk @@ -110,23 +110,32 @@ $(FIRRTL_FILE) $(ANNO_FILE) &: $(SCALA_SOURCES) $(sim_files) $(SCALA_BUILDTOOL_D --top-module $(MODEL_PACKAGE).$(MODEL) \ --legacy-configs $(CONFIG_PACKAGE):$(CONFIG) \ $(EXTRA_CHISEL_OPTIONS)) - sed -i '1d' $(ANNO_FILE) - echo "[" >> t.json - echo "{" >> t.json - echo " \"class\": \"sifive.enterprise.firrtl.ModuleHierarchyAnnotation\"," >> t.json - echo " \"filename\": \"./mod-he.json\"" >> t.json - echo "}," >> t.json - mv $(ANNO_FILE) t2.json - cat t.json t2.json > $(ANNO_FILE) - rm t.json t2.json + +$(FINAL_ANNO_FILE) $(FIRTOOL_EXTRA_ANNO_FILE): $(ANNO_FILE) + echo " \ + [\ + {\ + \"class\":\"sifive.enterprise.firrtl.MarkDUTAnnotation\",\ + \"target\":\"~$(MODEL)|$(TOP)\"\ + },\ + {\ + \"class\": \"sifive.enterprise.firrtl.TestHarnessHierarchyAnnotation\",\ + \"filename\": \"$(FIRTOOL_TB_MOD_HIER_JSON)\"\ + },\ + {\ + \"class\": \"sifive.enterprise.firrtl.ModuleHierarchyAnnotation\",\ + \"filename\": \"$(FIRTOOL_MOD_HIER_JSON)\"\ + } + ]" > $(FIRTOOL_EXTRA_ANNO_FILE) + jq -s '[.[][]]' $(ANNO_FILE) $(FIRTOOL_EXTRA_ANNO_FILE) > $@ .PHONY: firrtl -firrtl: $(FIRRTL_FILE) +firrtl: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) ######################################################################################### # create verilog files rules and variables ######################################################################################### -CIRCT_TARGETS = $(VSRC_SMEMS_CONF) $(VSRC_MODH_JSON) +CIRCT_TARGETS = $(TOP_SMEMS_CONF) $(FIRTOOL_MOD_HIER_JSON) $(FIRTOOL_TB_MOD_HIER_JSON) # DOC include start: FirrtlCompiler $(TOP_TARGETS) $(HARNESS_TARGETS) &: $(FIRRTL_FILE) $(ANNO_FILE) $(VLOG_SOURCES) @@ -156,12 +165,12 @@ $(TOP_TARGETS) $(HARNESS_TARGETS) &: $(FIRRTL_FILE) $(ANNO_FILE) $(VLOG_SOURCES) $(CIRCT_TARGETS): firrtl_temp @echo "" > /dev/null -firrtl_temp: $(FIRRTL_FILE) $(ANNO_FILE) $(VLOG_SOURCES) +firrtl_temp: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(VLOG_SOURCES) $(call run_scala_main,tapeout,barstools.tapeout.transforms.GenerateTop,\ --input-file $(FIRRTL_FILE) \ - --annotation-file $(ANNO_FILE) \ - --out-fir-file $(INT_FIR) \ - --out-anno-file $(INT_ANNO) \ + --annotation-file $(FINAL_ANNO_FILE) \ + --out-fir-file $(SFC_FIRRTL_FILE) \ + --out-anno-file $(SFC_ANNO_FILE) \ --log-level $(FIRRTL_LOGLEVEL) \ --allow-unrecognized-annotations \ -X none \ @@ -173,25 +182,25 @@ firrtl_temp: $(FIRRTL_FILE) $(ANNO_FILE) $(VLOG_SOURCES) -warn-on-unprocessed-annotations \ -verify-each=false \ -dedup \ - --annotation-file=$(INT_ANNO) \ + --annotation-file=$(SFC_ANNO_FILE) \ --disable-annotation-classless \ --disable-annotation-unknown \ --lowering-options=disallowPackedArrays,emittedLineLength=8192,noAlwaysComb,disallowLocalVariables \ --repl-seq-mem \ --repl-seq-mem-circuit=$(MODEL) \ - --repl-seq-mem-file=$(VSRC_SMEMS_CONF) \ + --repl-seq-mem-file=$(TOP_SMEMS_CONF) \ --split-verilog \ - -o $(VSRC_DUMP) \ - $(INT_FIR) - sed -i 's/.*/& /' $(VSRC_SMEMS_CONF) + -o $(build_dir) \ + $(SFC_FIRRTL_FILE) + sed -i 's/.*/& /' $(TOP_SMEMS_CONF) # need trailing space for SFC macrocompiler # DOC include end: FirrtlCompiler -$(TOP_MODS_FILE) $(ALL_MODS_FILE): $(VSRC_MODH_JSON) $(VSRC_FILELIST) - $(base_dir)/scripts/dump-mods.py --dut-top $(TOP) --hier-json $(VSRC_MODH_JSON) --dut-mods $(TOP_MODS_FILE) --filelist $(VSRC_FILELIST) --build_dir $(VSRC_DUMP) - sed -e 's;^;$(VSRC_DUMP)/;' $(VSRC_FILELIST) > $(ALL_MODS_FILE) +$(TOP_MODS_FILELIST) $(ALL_MODS_FILELIST): $(FIRTOOL_TB_MOD_HIER_JSON) $(FIRTOOL_FILELIST) + $(base_dir)/scripts/dump-mods.py --dut-top $(TOP) --hier-json $(FIRTOOL_TB_MOD_HIER_JSON) --dut-mods $(TOP_MODS_FILELIST) --filelist $(FIRTOOL_FILELIST) --build_dir $(build_dir) + sed -e 's;^;$(build_dir)/;' $(FIRTOOL_FILELIST) > $(ALL_MODS_FILELIST) .PHONY: temp -temp: $(TOP_MODS_FILE) +temp: $(TOP_MODS_FILELIST) # This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs MACROCOMPILER_MODE ?= --mode synflops @@ -205,15 +214,15 @@ $(HARNESS_SMEMS_FILE) $(HARNESS_SMEMS_FIR) &: $(HARNESS_SMEMS_CONF) | $(TOP_SMEM ######################################################################################## # remove duplicate files and headers in list of simulation file inputs ######################################################################################## -$(sim_common_files): $(sim_files) $(ALL_MODS_FILE) $(VSRC_SMEMS_FILE) - sort -u $(sim_files) $(ALL_MODS_FILE) | grep -v '.*\.\(svh\|h\)$$' > $@ - echo "$(VSRC_SMEMS_FILE)" >> $@ +$(sim_common_files): $(sim_files) $(ALL_MODS_FILELIST) $(TOP_SMEMS_FILE) + sort -u $(sim_files) $(ALL_MODS_FILELIST) | grep -v '.*\.\(svh\|h\)$$' > $@ + echo "$(TOP_SMEMS_FILE)" >> $@ ######################################################################################### # helper rule to just make verilog files ######################################################################################### .PHONY: verilog -verilog: $(sim_vsrcs) +verilog: $(sim_common_files) ######################################################################################### # helper rules to run simulations diff --git a/conda-reqs/chipyard.yaml b/conda-reqs/chipyard.yaml index f750a966..cbce236b 100644 --- a/conda-reqs/chipyard.yaml +++ b/conda-reqs/chipyard.yaml @@ -61,6 +61,7 @@ dependencies: - lzop - qemu # from ucb-bar channel - https://github.com/ucb-bar/qemu-feedstock + - jq - bash-completion - sbt - ca-certificates diff --git a/conda-requirements-riscv-tools.yaml b/conda-requirements-riscv-tools.yaml new file mode 100644 index 00000000..cc7ec901 --- /dev/null +++ b/conda-requirements-riscv-tools.yaml @@ -0,0 +1,133 @@ +channels: + - ucb-bar + - conda-forge + - nodefaults + +dependencies: + # https://conda-forge.org/feedstock-outputs/ + # filterable list of all conda-forge packages + # https://conda-forge.org/#contribute + # instructions on adding a recipe + # https://docs.conda.io/projects/conda/en/latest/user-guide/concepts/pkg-specs.html#package-match-specifications + # documentation on package_spec syntax for constraining versions + + + # handy tool for introspecting package relationships and file ownership + # see https://github.com/rvalieris/conda-tree + - conda-tree + + # bundle FireSim driver with deps into installer shell-script + - constructor + + - gcc + - gxx + - sysroot_linux-64>=2.17 # needed to match pre-built CI XRT glibc version + - conda-gcc-specs + - binutils + + - dromajo # from ucb-bar channel - https://github.com/riscv-boom/dromajo + - riscv-tools # from ucb-bar channel - https://github.com/ucb-bar/riscv-tools-feedstock + + # firemarshal deps + - python>=3.8 + - bc + - patch + - which + - diffutils + - bash + - gzip + - bzip2 + - perl + - tar + - file + - findutils + - rsync + - psutil + - doit=0.35.0 + - gitpython + - humanfriendly + - e2fsprogs + - ctags + - bison + - flex + - expat + - make + - pyyaml + - unzip + - readline + - coreutils + - lzop + - qemu # from ucb-bar channel - https://github.com/ucb-bar/qemu-feedstock + + - jq + - bash-completion + - sbt + - ca-certificates + - mosh + - gmp + - mpfr + - mpc + - zlib + - vim + - git + - openjdk + - gengetopt + - libffi + - expat + - libusb1 + - ncurses + - cmake + - graphviz + - expect + - dtc + - verilator==4.226 + - screen + - elfutils + - libdwarf-dev==0.0.0.20190110_28_ga81397fc4 # from ucb-bar channel - using mainline libdwarf-feedstock + - conda-lock>=1 + - wget + - sed + - autoconf + + # clang-format for driver coding style enforcement. + - clang-format + - clang-tools + + # python packages + # While it is possible to install using pip after creating the + # conda environment, pip's dependency resolution can conflict with + # conda and create broken environments. It's best to use the conda + # packages so that the environment is consistent + - boto3==1.20.21 + - colorama==0.4.3 + - argcomplete==1.12.3 + - python-graphviz==0.19 + - pyparsing==3.0.6 + - numpy==1.19.5 + - kiwisolver==1.3.1 + - matplotlib-base==3.3.4 + - pandas==1.1.5 + - awscli==1.22.21 + - pytest==6.2.5 + - pytest-dependency==0.5.1 + - pytest-mock==3.7.0 + - moto==3.1.0 + - pyyaml==5.4.1 + - mypy==0.931 + - types-pyyaml==6.0.4 + - boto3-stubs==1.21.6 + - botocore-stubs==1.24.7 + - mypy-boto3-s3==1.21.0 + - pip + - pip: + - fab-classic==1.19.1 + - mypy-boto3-ec2==1.21.9 + - sure==2.0.0 + - pylddwrap==1.2.1 + + # doc requirements + - sphinx + - pygments + - sphinx-autobuild + - sphinx_rtd_theme + - docutils diff --git a/variables.mk b/variables.mk index 45ebb5c3..11dbf3d6 100644 --- a/variables.mk +++ b/variables.mk @@ -145,23 +145,24 @@ endif FIRRTL_FILE ?= $(build_dir)/$(long_name).fir ANNO_FILE ?= $(build_dir)/$(long_name).anno.json +FIRTOOL_EXTRA_ANNO_FILE ?= $(build_dir)/$(long_name).extrafirtool.anno.json +FINAL_ANNO_FILE ?= $(build_dir)/$(long_name).appended.anno.json -INT_FIR ?= $(build_dir)/$(long_name).intermediate.fir -INT_ANNO ?= $(build_dir)/$(long_name).intermediate.anno.json +SFC_FIRRTL_FILE ?= $(build_dir)/$(long_name).sfc.fir +SFC_ANNO_FILE ?= $(build_dir)/$(long_name).sfc.anno.json -VSRC_DUMP ?= $(build_dir) -VSRC_SMEMS_CONF ?= $(VSRC_DUMP)/$(long_name).mems.conf -VSRC_MODH_JSON ?= $(VSRC_DUMP)/mod-he.json +FIRTOOL_MOD_HIER_JSON ?= $(build_dir)/modulehierarchy.json +FIRTOOL_TB_MOD_HIER_JSON ?= $(build_dir)/tbmodulehierarchy.json -VSRC_FILELIST ?= $(VSRC_DUMP)/filelist.f -VSRC_BB_F ?= $(VSRC_DUMP)/firrtl_black_box_resource_files.json +TOP_SMEMS_CONF ?= $(build_dir)/$(long_name).mems.conf +TOP_SMEMS_FILE ?= $(build_dir)/$(long_name).mems.v +TOP_SMEMS_FIR ?= $(build_dir)/$(long_name).mems.fir -VSRC_SMEMS_FILE ?= $(VSRC_DUMP)/$(long_name).mems.v -VSRC_SMEMS_FIR ?= $(VSRC_DUMP)/$(long_name).mems.fir - -# top only modules -TOP_MODS_FILE ?= $(VSRC_DUMP)/$(long_name).top.f -ALL_MODS_FILE ?= $(VSRC_DUMP)/$(long_name).all.f +FIRTOOL_FILELIST ?= $(build_dir)/filelist.f +# all module files to include (includes top modules) +ALL_MODS_FILELIST ?= $(build_dir)/$(long_name).all.f +# top module files to include +TOP_MODS_FILELIST ?= $(build_dir)/$(long_name).top.f BOOTROM_FILES ?= bootrom.rv64.img bootrom.rv32.img BOOTROM_TARGETS ?= $(addprefix $(build_dir)/, $(BOOTROM_FILES)) @@ -232,18 +233,6 @@ binary_hex= $(sim_out_name).loadmem_hex gen_dir=$(sim_dir)/generated-src build_dir=$(gen_dir)/$(long_name) -######################################################################################### -# vsrcs needed to run projects -######################################################################################### -rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc - -######################################################################################### -# sources needed to run simulators -######################################################################################### -sim_vsrcs = \ - $(VSRC_SMEMS_FILE) \ - $(VSRC_MODH_JSON) - ######################################################################################### # assembly/benchmark variables #########################################################################################