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Use Chain for dsptools example.

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Rename examples, bump dsptools to master, and incorporate feedback.
This commit is contained in:
Paul Rigge
2020-05-26 23:00:37 +00:00
parent a6e96b6496
commit e6984e412b
14 changed files with 104 additions and 97 deletions
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2
generators/chipyard/src/main/scala/DigitalTop.scala
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@@ -23,7 +23,7 @@ class DigitalTop(implicit p: Parameters) extends System
with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim
with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget
with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget
with chipyard.example.CanHavePeripheryFIR // Enables optionally adding the DSPTools FIR example widget
with chipyard.example.CanHavePeripheryStreamingFIR // Enables optionally adding the DSPTools FIR example widget
with chipyard.example.CanHavePeripheryStreamingPassthrough // Enables optionally adding the DSPTools streaming-passthrough example widget
with nvidia.blocks.dla.CanHavePeripheryNVDLA // Enables optionally having an NVDLA
{

8
generators/chipyard/src/main/scala/config/RocketConfigs.scala
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@@ -427,7 +427,7 @@ class RingSystemBusRocketConfig extends Config(
// DOC include end: RingSystemBusRocket
class StreamingPassthroughRocketConfig extends Config(
new chipyard.example.WithStreamingPassthrough ++ // use top with tilelink-controlled passthrough
new chipyard.example.WithStreamingPassthrough ++ // use top with tilelink-controlled streaming passthrough
new chipyard.iobinders.WithUARTAdapter ++
new chipyard.iobinders.WithTieOffInterrupts ++
new chipyard.iobinders.WithBlackBoxSimMem ++
@@ -445,9 +445,9 @@ class StreamingPassthroughRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
// DOC include start: FIRRocketConfig
class FIRRocketConfig extends Config (
new chipyard.example.WithFIR ++ // use top with tilelink-controlled FIR
// DOC include start: StreamingFIRRocketConfig
class StreamingFIRRocketConfig extends Config (
new chipyard.example.WithStreamingFIR ++ // use top with tilelink-controlled streaming FIR
new chipyard.iobinders.WithUARTAdapter ++
new chipyard.iobinders.WithTieOffInterrupts ++
new chipyard.iobinders.WithBlackBoxSimMem ++

54
generators/chipyard/src/main/scala/example/dsptools/DspBlocks.scala
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@@ -18,11 +18,11 @@ import freechips.rocketchip.subsystem._
* @param streamParameters parameters for the stream node
* @param p
*/
abstract class WriteQueue
abstract class WriteQueue[D, U, E, O, B <: Data]
(
val depth: Int = 8,
val depth: Int,
val streamParameters: AXI4StreamMasterParameters = AXI4StreamMasterParameters()
)(implicit p: Parameters) extends LazyModule with HasCSR {
)(implicit p: Parameters) extends DspBlock[D, U, E, O, B] with HasCSR {
// stream node, output only
val streamNode = AXI4StreamMasterNode(streamParameters)
@@ -58,12 +58,10 @@ abstract class WriteQueue
* @param beatBytes beatBytes of TL interface
* @param p
*/
class TLWriteQueue
(
depth: Int = 8,
csrAddress: AddressSet = AddressSet(0x2000, 0xff),
beatBytes: Int = 8,
)(implicit p: Parameters) extends WriteQueue(depth) with TLHasCSR {
class TLWriteQueue (depth: Int, csrAddress: AddressSet, beatBytes: Int)
(implicit p: Parameters) extends WriteQueue[
TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle
](depth) with TLHasCSR {
val devname = "tlQueueIn"
val devcompat = Seq("ucb-art", "dsptools")
val device = new SimpleDevice(devname, devcompat) {
@@ -76,6 +74,17 @@ class TLWriteQueue
override val mem = Some(TLRegisterNode(address = Seq(csrAddress), device = device, beatBytes = beatBytes))
}
object TLWriteQueue {
def apply(
depth: Int = 8,
csrAddress: AddressSet = AddressSet(0x2000, 0xff),
beatBytes: Int = 8,
)(implicit p: Parameters) = {
val writeQueue = LazyModule(new TLWriteQueue(depth = depth, csrAddress = csrAddress, beatBytes = beatBytes))
writeQueue
}
}
/**
* The streaming interface adds elements into the queue.
* The memory interface can read elements out of the queue.
@@ -83,11 +92,11 @@ class TLWriteQueue
* @param streamParameters parameters for the stream node
* @param p
*/
abstract class ReadQueue
abstract class ReadQueue[D, U, E, O, B <: Data]
(
val depth: Int = 8,
val depth: Int,
val streamParameters: AXI4StreamSlaveParameters = AXI4StreamSlaveParameters()
)(implicit p: Parameters) extends LazyModule with HasCSR {
)(implicit p: Parameters) extends DspBlock[D, U, E, O, B] with HasCSR {
val streamNode = AXI4StreamSlaveNode(streamParameters)
lazy val module = new LazyModuleImp(this) {
@@ -126,12 +135,10 @@ abstract class ReadQueue
* @param beatBytes beatBytes of TL interface
* @param p
*/
class TLReadQueue
(
depth: Int = 8,
csrAddress: AddressSet = AddressSet(0x2100, 0xff),
beatBytes: Int = 8
)(implicit p: Parameters) extends ReadQueue(depth) with TLHasCSR {
class TLReadQueue( depth: Int, csrAddress: AddressSet, beatBytes: Int)
(implicit p: Parameters) extends ReadQueue[
TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle
](depth) with TLHasCSR {
val devname = "tlQueueOut"
val devcompat = Seq("ucb-art", "dsptools")
val device = new SimpleDevice(devname, devcompat) {
@@ -142,5 +149,14 @@ class TLReadQueue
}
// make diplomatic TL node for regmap
override val mem = Some(TLRegisterNode(address = Seq(csrAddress), device = device, beatBytes = beatBytes))
}
object TLReadQueue {
def apply(
depth: Int = 8,
csrAddress: AddressSet = AddressSet(0x2100, 0xff),
beatBytes: Int = 8)(implicit p: Parameters) = {
val readQueue = LazyModule(new TLReadQueue(depth = depth, csrAddress = csrAddress, beatBytes = beatBytes))
readQueue
}
}

31
generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala
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@@ -188,30 +188,27 @@ GenericFIRBlock[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEd
// DOC include start: TLGenericFIRChain chisel
class TLGenericFIRChain[T<:Data:Ring] (genIn: T, genOut: T, coeffs: Seq[T], params: GenericFIRParams)(implicit p: Parameters)
extends LazyModule {
val writeQueue = LazyModule(new TLWriteQueue(params.depth, AddressSet(params.writeAddress, 0xff)))
val fir = LazyModule(new TLGenericFIRBlock(genIn, genOut, coeffs))
val readQueue = LazyModule(new TLReadQueue(params.depth, AddressSet(params.readAddress, 0xff)))
// connect streamNodes of queues and FIR
readQueue.streamNode := fir.streamNode := writeQueue.streamNode
lazy val module = new LazyModuleImp(this)
}
extends TLChain(Seq(
TLWriteQueue(params.depth, AddressSet(params.writeAddress, 0xff))(_),
{ implicit p: Parameters =>
val fir = LazyModule(new TLGenericFIRBlock(genIn, genOut, coeffs))
fir
},
TLReadQueue(params.depth, AddressSet(params.readAddress, 0xff))(_)
))
// DOC include end: TLGenericFIRChain chisel
// DOC include start: CanHavePeripheryFIR chisel
trait CanHavePeripheryFIR extends BaseSubsystem {
val fir = p(GenericFIRKey) match {
trait CanHavePeripheryStreamingFIR extends BaseSubsystem {
val streamingFIR = p(GenericFIRKey) match {
case Some(params) => {
val fir = LazyModule(new TLGenericFIRChain(
val streamingFIR = LazyModule(new TLGenericFIRChain(
genIn = FixedPoint(8.W, 3.BP),
genOut = FixedPoint(8.W, 3.BP),
coeffs = Seq(1.F(0.BP), 2.F(0.BP), 3.F(0.BP)),
params = params))
pbus.toVariableWidthSlave(Some("firWrite")) { fir.writeQueue.mem.get }
pbus.toVariableWidthSlave(Some("firRead")) { fir.readQueue.mem.get }
pbus.toVariableWidthSlave(Some("streamingFIR")) { streamingFIR.mem.get := TLFIFOFixer() }
Some(streamingFIR)
}
case None => None
}
@@ -222,7 +219,7 @@ trait CanHavePeripheryFIR extends BaseSubsystem {
* Mixin to add FIR to rocket config
*/
// DOC include start: WithFIR
class WithFIR extends Config((site, here, up) => {
class WithStreamingFIR extends Config((site, here, up) => {
case GenericFIRKey => Some(GenericFIRParams(depth = 8))
})
// DOC include end: WithFIR

28
generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala
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@@ -121,27 +121,21 @@ with TLDspBlock
* @tparam T Type parameter for passthrough, i.e. FixedPoint or DspReal
*/
class TLStreamingPassthroughChain[T<:Data:Ring](params: StreamingPassthroughParams, proto: T)(implicit p: Parameters)
extends LazyModule {
// instantiate lazy modules
val writeQueue = LazyModule(new TLWriteQueue(params.depth, AddressSet(params.writeAddress, 0xff)))
val passthrough = LazyModule(new TLStreamingPassthroughBlock(proto))
val readQueue = LazyModule(new TLReadQueue(params.depth, AddressSet(params.readAddress, 0xff)))
// connect streamNodes of queues and passthrough
readQueue.streamNode := passthrough.streamNode := writeQueue.streamNode
lazy val module = new LazyModuleImp(this)
}
extends TLChain(Seq(
TLWriteQueue(params.depth, AddressSet(params.writeAddress, 0xff))(_),
{ implicit p: Parameters => {
val streamingPassthrough = LazyModule(new TLStreamingPassthroughBlock(proto))
streamingPassthrough
}},
TLReadQueue(params.depth, AddressSet(params.readAddress, 0xff))(_)
))
trait CanHavePeripheryStreamingPassthrough { this: BaseSubsystem =>
val passthrough = p(StreamingPassthroughKey) match {
case Some(params) => {
val passthrough = LazyModule(new TLStreamingPassthroughChain(params, UInt(32.W)))
pbus.toVariableWidthSlave(Some("passthroughWrite")) { passthrough.writeQueue.mem.get }
pbus.toVariableWidthSlave(Some("passthroughRead")) { passthrough.readQueue.mem.get }
Some(passthrough)
val streamingPassthroughChain = LazyModule(new TLStreamingPassthroughChain(params, UInt(32.W)))
pbus.toVariableWidthSlave(Some("streamingPassthrough")) { streamingPassthroughChain.mem.get := TLFIFOFixer() }
Some(streamingPassthroughChain)
}
case None => None
}