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Renaming updates | Have FireSim clocks request frequency by default

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This commit is contained in:
Abraham Gonzalez
2021-03-08 23:43:00 +00:00
parent 6ab8f8f8fc
commit e4ccfe1bb9
3 changed files with 23 additions and 13 deletions
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2
generators/chipyard/src/main/scala/HarnessBinders.scala
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@@ -160,7 +160,7 @@ class WithSimAXIMemOverSerialTL extends OverrideHarnessBinder({
val harnessMultiClockAXIRAM = SerialAdapter.connectHarnessMultiClockAXIRAM(
system.serdesser.get,
port,
p(HarnessClockInstantiatorKey).getClockBundleWire("mem_over_serial_tl_clock", memFreq),
p(HarnessClockInstantiatorKey).getClockBundle("mem_over_serial_tl_clock", memFreq),
th.harnessReset)
val success = SerialAdapter.connectSimSerial(harnessMultiClockAXIRAM.module.io.tsi_ser, port.clock, th.harnessReset.asBool)
when (success) { th.success := true.B }

4
generators/chipyard/src/main/scala/TestHarness.scala
View File

@@ -34,7 +34,7 @@ class HarnessClockInstantiator {
private var _clockMap: HashMap[String, (Double, ClockBundle)] = HashMap.empty
// request a clock bundle at a particular frequency
def getClockBundleWire(name: String, freqRequested: Double): ClockBundle = {
def getClockBundle(name: String, freqRequested: Double): ClockBundle = {
val clockBundle = Wire(new ClockBundle(ClockBundleParameters()))
_clockMap(name) = (freqRequested, clockBundle)
clockBundle
@@ -95,7 +95,7 @@ class TestHarness(implicit val p: Parameters) extends Module with HasHarnessSign
case d: HasReferenceClockFreq => d.refClockFreqMHz.getOrElse(p(DefaultClockFrequencyKey))
case _ => p(DefaultClockFrequencyKey)
}
val refClkBundle = p(HarnessClockInstantiatorKey).getClockBundleWire("buildtop_reference_clock", freqMHz * (1000 * 1000))
val refClkBundle = p(HarnessClockInstantiatorKey).getClockBundle("buildtop_reference_clock", freqMHz * (1000 * 1000))
harnessClock := refClkBundle.clock
harnessReset := WireInit(refClkBundle.reset)