From e47cf92139a409902e754e43b9782277f56839b8 Mon Sep 17 00:00:00 2001
From: Edward Wang <edward.c.wang@compdigitec.com>
Date: Mon, 31 Jul 2017 15:41:59 -0700
Subject: [PATCH] Move HasNoLibTestGenerator out of SynFlops

---
 macros/src/test/scala/MacroCompilerSpec.scala | 16 ++++++++++++++++
 macros/src/test/scala/SynFlops.scala          | 16 ----------------
 2 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/macros/src/test/scala/MacroCompilerSpec.scala b/macros/src/test/scala/MacroCompilerSpec.scala
index fb70c561..8a8f542f 100644
--- a/macros/src/test/scala/MacroCompilerSpec.scala
+++ b/macros/src/test/scala/MacroCompilerSpec.scala
@@ -313,6 +313,22 @@ ${generateFooter}
     val output = generateOutput()
 }
 
+// Use this trait for tests that invoke the memory compiler without lib.
+trait HasNoLibTestGenerator extends HasSimpleTestGenerator {
+  this: MacroCompilerSpec with HasSRAMGenerator =>
+
+    // If there isn't a lib, then the "lib" will become a FIRRTL "mem", which
+    // in turn becomes synthesized flops.
+    // Therefore, make "lib" width/depth equal to the mem.
+    override lazy val libDepth = memDepth
+    override lazy val libWidth = memWidth
+    // Do the same for port names.
+    override lazy val libPortPrefix = memPortPrefix
+
+    // If there is no lib, don't generate a body.
+    override def generateBody = ""
+}
+
 //~ class RocketChipTest extends MacroCompilerSpec {
   //~ val mem = new File(macroDir, "rocketchip.json")
   //~ val lib = new File(macroDir, "mylib.json")
diff --git a/macros/src/test/scala/SynFlops.scala b/macros/src/test/scala/SynFlops.scala
index 0394dc40..f273c29e 100644
--- a/macros/src/test/scala/SynFlops.scala
+++ b/macros/src/test/scala/SynFlops.scala
@@ -1,21 +1,5 @@
 package barstools.macros
 
-// Use this trait for tests that invoke the memory compiler without lib.
-trait HasNoLibTestGenerator extends HasSimpleTestGenerator {
-  this: MacroCompilerSpec with HasSRAMGenerator =>
-
-    // If there isn't a lib, then the "lib" will become a FIRRTL "mem", which
-    // in turn becomes synthesized flops.
-    // Therefore, make "lib" width/depth equal to the mem.
-    override lazy val libDepth = memDepth
-    override lazy val libWidth = memWidth
-    // Do the same for port names.
-    override lazy val libPortPrefix = memPortPrefix
-
-    // If there is no lib, don't generate a body.
-    override def generateBody = ""
-}
-
 // Test flop synthesis of the memory compiler.
 
 trait HasSynFlopsTestGenerator extends HasSimpleTestGenerator {