diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala
index d8350626..a3f637d0 100644
--- a/generators/firechip/src/main/scala/TargetConfigs.scala
+++ b/generators/firechip/src/main/scala/TargetConfigs.scala
@@ -76,6 +76,10 @@ class WithBoomL2TLBs(entries: Int) extends Config((site, here, up) => {
   ))
 })
 
+class WithBoomEnableTrace extends Config((site, here, up) => {
+  case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true))
+})
+
 // Disables clock-gating; doesn't play nice with our FAME-1 pass
 class WithoutClockGating extends Config((site, here, up) => {
   case DebugModuleParams => up(DebugModuleParams, site).copy(clockGate = false)
@@ -170,6 +174,7 @@ class FireSimBoomConfig extends Config(
   new WithUARTKey ++
   new WithNICKey ++
   new WithBlockDevice ++
+  new WithBoomEnableTrace ++
   new WithBoomL2TLBs(1024) ++
   new WithoutClockGating ++
   new WithDefaultMemModel ++
diff --git a/generators/firechip/src/main/scala/TargetMixins.scala b/generators/firechip/src/main/scala/TargetMixins.scala
index d7714527..55761233 100644
--- a/generators/firechip/src/main/scala/TargetMixins.scala
+++ b/generators/firechip/src/main/scala/TargetMixins.scala
@@ -46,7 +46,8 @@ trait HasTraceIOImp extends LazyModuleImp {
       if (p(PrintTracePort)) {
         withClockAndReset(node.bundle.head.clock, node.bundle.head.reset) {
           val traceprint = WireDefault(0.U(512.W))
-          traceprint := b.io.traces.asUInt
+          // The reverse is here to match the behavior the Cat used in the bridge
+          traceprint := b.io.traces.reverse.asUInt
           printf(s"TRACEPORT ${idx}: %x\n", traceprint)
         }
       }