From e3d5e4d3ad361771e3d656da0b1e80ddfabc5635 Mon Sep 17 00:00:00 2001 From: Edward Wang Date: Fri, 28 Jul 2017 15:29:03 -0700 Subject: [PATCH] Refactor execution of the compiler from the check --- macros/src/test/scala/MacroCompilerSpec.scala | 31 +++-- macros/src/test/scala/SimpleSplitDepth.scala | 75 ++++-------- macros/src/test/scala/SimpleSplitWidth.scala | 108 ++++++------------ 3 files changed, 83 insertions(+), 131 deletions(-) diff --git a/macros/src/test/scala/MacroCompilerSpec.scala b/macros/src/test/scala/MacroCompilerSpec.scala index 87ff3651..65b6f213 100644 --- a/macros/src/test/scala/MacroCompilerSpec.scala +++ b/macros/src/test/scala/MacroCompilerSpec.scala @@ -52,14 +52,28 @@ abstract class MacroCompilerSpec extends org.scalatest.FlatSpec with org.scalate mdf.macrolib.Utils.writeMDFToPath(Some(concat(memPrefix, mem)), mems) } - // Execute the macro compiler and compare FIRRTL outputs after reparsing output. - def execute(memFile: String, libFile: Option[String], synflops: Boolean, output: String): Unit = { - execute(Some(memFile), libFile, synflops, output) + // Convenience function for running both compile, execute, and test at once. + def compileExecuteAndTest(mem: String, lib: String, v: String, output: String, synflops: Boolean = false): Unit = { + compile(mem, lib, v, synflops) + val result = execute(mem, lib, synflops) + test(result, output) } - def execute(memFile: String, libFile: String, synflops: Boolean, output: String): Unit = { - execute(Some(memFile), Some(libFile), synflops, output) + + // Compare FIRRTL outputs after reparsing output with ScalaTest ("should be"). + def test(result: Circuit, output: String): Unit = { + val gold = RemoveEmpty run parse(output) + (result.serialize) should be (gold.serialize) } - def execute(memFile: Option[String], libFile: Option[String], synflops: Boolean, output: String): Unit = { + + // Execute the macro compiler and returns a Circuit containing the output of + // the memory compiler. + def execute(memFile: String, libFile: Option[String], synflops: Boolean): Circuit = { + execute(Some(memFile), libFile, synflops) + } + def execute(memFile: String, libFile: String, synflops: Boolean): Circuit = { + execute(Some(memFile), Some(libFile), synflops) + } + def execute(memFile: Option[String], libFile: Option[String], synflops: Boolean): Circuit = { var mem_full = concat(memPrefix, memFile) var lib_full = concat(libPrefix, libFile) @@ -75,9 +89,8 @@ abstract class MacroCompilerSpec extends org.scalatest.FlatSpec with org.scalate new MacroCompilerPass(Some(mems), libs), new SynFlopsPass(synflops, libs getOrElse mems), RemoveEmpty) - val result = (passes foldLeft circuit)((c, pass) => pass run c) - val gold = RemoveEmpty run parse(output) - (result.serialize) should be (gold.serialize) + val result: Circuit = (passes foldLeft circuit)((c, pass) => pass run c) + result } // Helper method to deal with String + Option[String] diff --git a/macros/src/test/scala/SimpleSplitDepth.scala b/macros/src/test/scala/SimpleSplitDepth.scala index 46b4420a..2a5c312c 100644 --- a/macros/src/test/scala/SimpleSplitDepth.scala +++ b/macros/src/test/scala/SimpleSplitDepth.scala @@ -84,8 +84,7 @@ class SplitDepth4096x32_rw extends MacroCompilerSpec with HasSRAMGenerator with override lazy val memDepth = 4096 override lazy val libDepth = 1024 - compile(mem, lib, v, false) - execute(mem, lib, false, output) + compileExecuteAndTest(mem, lib, v, output) } class SplitDepth4096x16_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator { @@ -93,8 +92,7 @@ class SplitDepth4096x16_rw extends MacroCompilerSpec with HasSRAMGenerator with override lazy val memDepth = 4096 override lazy val libDepth = 1024 - compile(mem, lib, v, false) - execute(mem, lib, false, output) + compileExecuteAndTest(mem, lib, v, output) } class SplitDepth32768x8_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator { @@ -102,8 +100,7 @@ class SplitDepth32768x8_rw extends MacroCompilerSpec with HasSRAMGenerator with override lazy val memDepth = 32768 override lazy val libDepth = 1024 - compile(mem, lib, v, false) - execute(mem, lib, false, output) + compileExecuteAndTest(mem, lib, v, output) } class SplitDepth4096x8_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator { @@ -111,8 +108,7 @@ class SplitDepth4096x8_rw extends MacroCompilerSpec with HasSRAMGenerator with H override lazy val memDepth = 4096 override lazy val libDepth = 1024 - compile(mem, lib, v, false) - execute(mem, lib, false, output) + compileExecuteAndTest(mem, lib, v, output) } class SplitDepth2048x8_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator { @@ -120,8 +116,7 @@ class SplitDepth2048x8_rw extends MacroCompilerSpec with HasSRAMGenerator with H override lazy val memDepth = 2048 override lazy val libDepth = 1024 - compile(mem, lib, v, false) - execute(mem, lib, false, output) + compileExecuteAndTest(mem, lib, v, output) } class SplitDepth1024x8_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator { @@ -129,8 +124,7 @@ class SplitDepth1024x8_rw extends MacroCompilerSpec with HasSRAMGenerator with H override lazy val memDepth = 1024 override lazy val libDepth = 1024 - compile(mem, lib, v, false) - execute(mem, lib, false, output) + compileExecuteAndTest(mem, lib, v, output) } // Non power of two @@ -139,8 +133,7 @@ class SplitDepth2000x8_rw extends MacroCompilerSpec with HasSRAMGenerator with H override lazy val memDepth = 2000 override lazy val libDepth = 1024 - compile(mem, lib, v, false) - execute(mem, lib, false, output) + compileExecuteAndTest(mem, lib, v, output) } class SplitDepth2049x8_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator { @@ -148,8 +141,7 @@ class SplitDepth2049x8_rw extends MacroCompilerSpec with HasSRAMGenerator with H override lazy val memDepth = 2049 override lazy val libDepth = 1024 - compile(mem, lib, v, false) - execute(mem, lib, false, output) + compileExecuteAndTest(mem, lib, v, output) } // Masked RAMs @@ -162,8 +154,7 @@ class SplitDepth2048x32_mrw_lib32 extends MacroCompilerSpec with HasSRAMGenerato override lazy val memMaskGran = Some(32) override lazy val libMaskGran = Some(32) - compile(mem, lib, v, false) - execute(mem, lib, false, output) + compileExecuteAndTest(mem, lib, v, output) } class SplitDepth2048x8_mrw_lib8 extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator { @@ -173,8 +164,7 @@ class SplitDepth2048x8_mrw_lib8 extends MacroCompilerSpec with HasSRAMGenerator override lazy val memMaskGran = Some(8) override lazy val libMaskGran = Some(8) - compile(mem, lib, v, false) - execute(mem, lib, false, output) + compileExecuteAndTest(mem, lib, v, output) } // Non-bit level mask @@ -186,8 +176,7 @@ class SplitDepth2048x64_mrw_mem32_lib8 extends MacroCompilerSpec with HasSRAMGen override lazy val libMaskGran = Some(8) it should "be enabled when non-bitmasked memories are supported" is (pending) - //compile(mem, lib, v, false) - //execute(mem, lib, false, output) + //compileExecuteAndTest(mem, lib, v, output) } // Bit level mask @@ -198,8 +187,7 @@ class SplitDepth2048x32_mrw_mem16_lib1 extends MacroCompilerSpec with HasSRAMGen override lazy val memMaskGran = Some(16) override lazy val libMaskGran = Some(1) - compile(mem, lib, v, false) - execute(mem, lib, false, output) + compileExecuteAndTest(mem, lib, v, output) } class SplitDepth2048x32_mrw_mem8_lib1 extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator { @@ -209,8 +197,7 @@ class SplitDepth2048x32_mrw_mem8_lib1 extends MacroCompilerSpec with HasSRAMGene override lazy val memMaskGran = Some(8) override lazy val libMaskGran = Some(1) - compile(mem, lib, v, false) - execute(mem, lib, false, output) + compileExecuteAndTest(mem, lib, v, output) } class SplitDepth2048x32_mrw_mem4_lib1 extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator { @@ -220,8 +207,7 @@ class SplitDepth2048x32_mrw_mem4_lib1 extends MacroCompilerSpec with HasSRAMGene override lazy val memMaskGran = Some(4) override lazy val libMaskGran = Some(1) - compile(mem, lib, v, false) - execute(mem, lib, false, output) + compileExecuteAndTest(mem, lib, v, output) } class SplitDepth2048x32_mrw_mem2_lib1 extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator { @@ -231,8 +217,7 @@ class SplitDepth2048x32_mrw_mem2_lib1 extends MacroCompilerSpec with HasSRAMGene override lazy val memMaskGran = Some(2) override lazy val libMaskGran = Some(1) - compile(mem, lib, v, false) - execute(mem, lib, false, output) + compileExecuteAndTest(mem, lib, v, output) } // Non-powers of 2 mask sizes @@ -244,8 +229,7 @@ class SplitDepth2048x32_mrw_mem3_lib1 extends MacroCompilerSpec with HasSRAMGene override lazy val libMaskGran = Some(1) it should "be enabled when non-power of two masks are supported" is (pending) - //compile(mem, lib, v, false) - //execute(mem, lib, false, output) + //compileExecuteAndTest(mem, lib, v, output) } class SplitDepth2048x32_mrw_mem7_lib1 extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator { @@ -256,8 +240,7 @@ class SplitDepth2048x32_mrw_mem7_lib1 extends MacroCompilerSpec with HasSRAMGene override lazy val libMaskGran = Some(1) it should "be enabled when non-power of two masks are supported" is (pending) - //compile(mem, lib, v, false) - //execute(mem, lib, false, output) + //compileExecuteAndTest(mem, lib, v, output) } class SplitDepth2048x32_mrw_mem9_lib1 extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator { @@ -268,8 +251,7 @@ class SplitDepth2048x32_mrw_mem9_lib1 extends MacroCompilerSpec with HasSRAMGene override lazy val libMaskGran = Some(1) it should "be enabled when non-power of two masks are supported" is (pending) - //compile(mem, lib, v, false) - //execute(mem, lib, false, output) + //compileExecuteAndTest(mem, lib, v, output) } // Try an extra port @@ -327,8 +309,7 @@ circuit target_memory : defname = awesome_lib_mem """ - compile(mem, lib, v, false) - execute(mem, lib, false, output) + compileExecuteAndTest(mem, lib, v, output) } // Split read and (non-masked) write ports (r+w). @@ -420,8 +401,7 @@ circuit target_memory : defname = awesome_lib_mem """ - compile(mem, lib, v, false) - execute(mem, lib, false, output) + compileExecuteAndTest(mem, lib, v, output) } "Non-masked regular lib; split mem" should "split fine" in { @@ -454,8 +434,7 @@ circuit target_memory : TODO """ - compile(mem, lib, v, false) - execute(mem, lib, false, output) + compileExecuteAndTest(mem, lib, v, output) } "Non-masked split lib; regular mem" should "split fine" in { @@ -489,8 +468,7 @@ TODO TODO """ - compile(mem, lib, v, false) - execute(mem, lib, false, output) + compileExecuteAndTest(mem, lib, v, output) } } @@ -589,8 +567,7 @@ circuit target_memory : defname = awesome_lib_mem """ - compile(mem, lib, v, false) - execute(mem, lib, false, output) + compileExecuteAndTest(mem, lib, v, output) } "Non-masked regular lib; split mem" should "split fine" in { @@ -623,8 +600,7 @@ circuit target_memory : TODO """ - compile(mem, lib, v, false) - execute(mem, lib, false, output) + compileExecuteAndTest(mem, lib, v, output) } "Non-masked split lib; regular mem" should "split fine" in { @@ -658,7 +634,6 @@ TODO TODO """ - compile(mem, lib, v, false) - execute(mem, lib, false, output) + compileExecuteAndTest(mem, lib, v, output) } } diff --git a/macros/src/test/scala/SimpleSplitWidth.scala b/macros/src/test/scala/SimpleSplitWidth.scala index 4a48c7be..b75b9fe9 100644 --- a/macros/src/test/scala/SimpleSplitWidth.scala +++ b/macros/src/test/scala/SimpleSplitWidth.scala @@ -85,8 +85,7 @@ class SplitWidth1024x128_rw extends MacroCompilerSpec with HasSRAMGenerator with override lazy val memWidth = 128 override lazy val libWidth = 8 - compile(mem, lib, v, false) - execute(mem, lib, false, output) + compileExecuteAndTest(mem, lib, v, output) } class SplitWidth1024x64_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator { @@ -94,8 +93,7 @@ class SplitWidth1024x64_rw extends MacroCompilerSpec with HasSRAMGenerator with override lazy val memWidth = 64 override lazy val libWidth = 8 - compile(mem, lib, v, false) - execute(mem, lib, false, output) + compileExecuteAndTest(mem, lib, v, output) } class SplitWidth1024x32_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator { @@ -103,8 +101,7 @@ class SplitWidth1024x32_rw extends MacroCompilerSpec with HasSRAMGenerator with override lazy val memWidth = 32 override lazy val libWidth = 8 - compile(mem, lib, v, false) - execute(mem, lib, false, output) + compileExecuteAndTest(mem, lib, v, output) } class SplitWidth1024x16_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator { @@ -112,8 +109,7 @@ class SplitWidth1024x16_rw extends MacroCompilerSpec with HasSRAMGenerator with override lazy val memWidth = 16 override lazy val libWidth = 8 - compile(mem, lib, v, false) - execute(mem, lib, false, output) + compileExecuteAndTest(mem, lib, v, output) } class SplitWidth1024x8_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator { @@ -121,8 +117,7 @@ class SplitWidth1024x8_rw extends MacroCompilerSpec with HasSRAMGenerator with H override lazy val memWidth = 8 override lazy val libWidth = 8 - compile(mem, lib, v, false) - execute(mem, lib, false, output) + compileExecuteAndTest(mem, lib, v, output) } // Try different widths against a base memory width of 16. @@ -131,8 +126,7 @@ class SplitWidth1024x128_lib16_rw extends MacroCompilerSpec with HasSRAMGenerato override lazy val memWidth = 128 override lazy val libWidth = 16 - compile(mem, lib, v, false) - execute(mem, lib, false, output) + compileExecuteAndTest(mem, lib, v, output) } class SplitWidth1024x64_lib16_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator { @@ -140,8 +134,7 @@ class SplitWidth1024x64_lib16_rw extends MacroCompilerSpec with HasSRAMGenerator override lazy val memWidth = 64 override lazy val libWidth = 16 - compile(mem, lib, v, false) - execute(mem, lib, false, output) + compileExecuteAndTest(mem, lib, v, output) } class SplitWidth1024x32_lib16_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator { @@ -149,8 +142,7 @@ class SplitWidth1024x32_lib16_rw extends MacroCompilerSpec with HasSRAMGenerator override lazy val memWidth = 32 override lazy val libWidth = 16 - compile(mem, lib, v, false) - execute(mem, lib, false, output) + compileExecuteAndTest(mem, lib, v, output) } class SplitWidth1024x16_lib16_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator { @@ -158,8 +150,7 @@ class SplitWidth1024x16_lib16_rw extends MacroCompilerSpec with HasSRAMGenerator override lazy val memWidth = 16 override lazy val libWidth = 16 - compile(mem, lib, v, false) - execute(mem, lib, false, output) + compileExecuteAndTest(mem, lib, v, output) } // Try different widths against a base memory width of 8 but depth 512 instead of 1024. @@ -168,8 +159,7 @@ class SplitWidth512x128_rw extends MacroCompilerSpec with HasSRAMGenerator with override lazy val memWidth = 128 override lazy val libWidth = 8 - compile(mem, lib, v, false) - execute(mem, lib, false, output) + compileExecuteAndTest(mem, lib, v, output) } class SplitWidth512x64_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator { @@ -177,8 +167,7 @@ class SplitWidth512x64_rw extends MacroCompilerSpec with HasSRAMGenerator with H override lazy val memWidth = 64 override lazy val libWidth = 8 - compile(mem, lib, v, false) - execute(mem, lib, false, output) + compileExecuteAndTest(mem, lib, v, output) } class SplitWidth512x32_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator { @@ -186,8 +175,7 @@ class SplitWidth512x32_rw extends MacroCompilerSpec with HasSRAMGenerator with H override lazy val memWidth = 32 override lazy val libWidth = 8 - compile(mem, lib, v, false) - execute(mem, lib, false, output) + compileExecuteAndTest(mem, lib, v, output) } class SplitWidth512x16_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator { @@ -195,8 +183,7 @@ class SplitWidth512x16_rw extends MacroCompilerSpec with HasSRAMGenerator with H override lazy val memWidth = 16 override lazy val libWidth = 8 - compile(mem, lib, v, false) - execute(mem, lib, false, output) + compileExecuteAndTest(mem, lib, v, output) } class SplitWidth512x8_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator { @@ -204,8 +191,7 @@ class SplitWidth512x8_rw extends MacroCompilerSpec with HasSRAMGenerator with Ha override lazy val memWidth = 8 override lazy val libWidth = 8 - compile(mem, lib, v, false) - execute(mem, lib, false, output) + compileExecuteAndTest(mem, lib, v, output) } // Try non-power of two widths against a base memory width of 8. @@ -214,8 +200,7 @@ class SplitWidth1024x67_rw extends MacroCompilerSpec with HasSRAMGenerator with override lazy val memWidth = 67 override lazy val libWidth = 8 - compile(mem, lib, v, false) - execute(mem, lib, false, output) + compileExecuteAndTest(mem, lib, v, output) } class SplitWidth1024x60_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator { @@ -223,8 +208,7 @@ class SplitWidth1024x60_rw extends MacroCompilerSpec with HasSRAMGenerator with override lazy val memWidth = 60 override lazy val libWidth = 8 - compile(mem, lib, v, false) - execute(mem, lib, false, output) + compileExecuteAndTest(mem, lib, v, output) } class SplitWidth1024x42_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator { @@ -232,8 +216,7 @@ class SplitWidth1024x42_rw extends MacroCompilerSpec with HasSRAMGenerator with override lazy val memWidth = 42 override lazy val libWidth = 8 - compile(mem, lib, v, false) - execute(mem, lib, false, output) + compileExecuteAndTest(mem, lib, v, output) } class SplitWidth1024x20_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator { @@ -241,8 +224,7 @@ class SplitWidth1024x20_rw extends MacroCompilerSpec with HasSRAMGenerator with override lazy val memWidth = 20 override lazy val libWidth = 8 - compile(mem, lib, v, false) - execute(mem, lib, false, output) + compileExecuteAndTest(mem, lib, v, output) } class SplitWidth1024x17_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator { @@ -250,8 +232,7 @@ class SplitWidth1024x17_rw extends MacroCompilerSpec with HasSRAMGenerator with override lazy val memWidth = 17 override lazy val libWidth = 8 - compile(mem, lib, v, false) - execute(mem, lib, false, output) + compileExecuteAndTest(mem, lib, v, output) } class SplitWidth1024x15_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator { @@ -259,8 +240,7 @@ class SplitWidth1024x15_rw extends MacroCompilerSpec with HasSRAMGenerator with override lazy val memWidth = 15 override lazy val libWidth = 8 - compile(mem, lib, v, false) - execute(mem, lib, false, output) + compileExecuteAndTest(mem, lib, v, output) } class SplitWidth1024x9_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator { @@ -268,8 +248,7 @@ class SplitWidth1024x9_rw extends MacroCompilerSpec with HasSRAMGenerator with H override lazy val memWidth = 9 override lazy val libWidth = 8 - compile(mem, lib, v, false) - execute(mem, lib, false, output) + compileExecuteAndTest(mem, lib, v, output) } // Try against a non-power of two base memory width. @@ -278,8 +257,7 @@ class SplitWidth1024x64_mem11_rw extends MacroCompilerSpec with HasSRAMGenerator override lazy val memWidth = 64 override lazy val libWidth = 11 - compile(mem, lib, v, false) - execute(mem, lib, false, output) + compileExecuteAndTest(mem, lib, v, output) } class SplitWidth1024x33_mem11_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator { @@ -287,8 +265,7 @@ class SplitWidth1024x33_mem11_rw extends MacroCompilerSpec with HasSRAMGenerator override lazy val memWidth = 33 override lazy val libWidth = 11 - compile(mem, lib, v, false) - execute(mem, lib, false, output) + compileExecuteAndTest(mem, lib, v, output) } class SplitWidth1024x16_mem11_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator { @@ -296,8 +273,7 @@ class SplitWidth1024x16_mem11_rw extends MacroCompilerSpec with HasSRAMGenerator override lazy val memWidth = 16 override lazy val libWidth = 11 - compile(mem, lib, v, false) - execute(mem, lib, false, output) + compileExecuteAndTest(mem, lib, v, output) } // Masked RAM @@ -309,8 +285,7 @@ class SplitWidth1024x8_memGran_8_libGran_1_rw extends MacroCompilerSpec with Has override lazy val memMaskGran = Some(8) override lazy val libMaskGran = Some(1) - compile(mem, lib, v, false) - execute(mem, lib, false, output) + compileExecuteAndTest(mem, lib, v, output) } class SplitWidth1024x16_memGran_8_libGran_1_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator { @@ -320,8 +295,7 @@ class SplitWidth1024x16_memGran_8_libGran_1_rw extends MacroCompilerSpec with Ha override lazy val memMaskGran = Some(8) override lazy val libMaskGran = Some(1) - compile(mem, lib, v, false) - execute(mem, lib, false, output) + compileExecuteAndTest(mem, lib, v, output) } class SplitWidth1024x16_memGran_8_libGran_8_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator { @@ -331,8 +305,7 @@ class SplitWidth1024x16_memGran_8_libGran_8_rw extends MacroCompilerSpec with Ha override lazy val memMaskGran = Some(8) override lazy val libMaskGran = Some(8) - compile(mem, lib, v, false) - execute(mem, lib, false, output) + compileExecuteAndTest(mem, lib, v, output) } class SplitWidth1024x128_memGran_8_libGran_1_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator { @@ -342,8 +315,7 @@ class SplitWidth1024x128_memGran_8_libGran_1_rw extends MacroCompilerSpec with H override lazy val memMaskGran = Some(8) override lazy val libMaskGran = Some(1) - compile(mem, lib, v, false) - execute(mem, lib, false, output) + compileExecuteAndTest(mem, lib, v, output) } class SplitWidth1024x16_memGran_4_libGran_1_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator { @@ -353,8 +325,7 @@ class SplitWidth1024x16_memGran_4_libGran_1_rw extends MacroCompilerSpec with Ha override lazy val memMaskGran = Some(4) override lazy val libMaskGran = Some(1) - compile(mem, lib, v, false) - execute(mem, lib, false, output) + compileExecuteAndTest(mem, lib, v, output) } class SplitWidth1024x16_memGran_2_libGran_1_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator { @@ -364,8 +335,7 @@ class SplitWidth1024x16_memGran_2_libGran_1_rw extends MacroCompilerSpec with Ha override lazy val memMaskGran = Some(2) override lazy val libMaskGran = Some(1) - compile(mem, lib, v, false) - execute(mem, lib, false, output) + compileExecuteAndTest(mem, lib, v, output) } class SplitWidth1024x16_memGran_16_libGran_1_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator { @@ -375,8 +345,7 @@ class SplitWidth1024x16_memGran_16_libGran_1_rw extends MacroCompilerSpec with H override lazy val memMaskGran = Some(16) override lazy val libMaskGran = Some(1) - compile(mem, lib, v, false) - execute(mem, lib, false, output) + compileExecuteAndTest(mem, lib, v, output) } // Non-masked mem, masked lib @@ -387,8 +356,7 @@ class SplitWidth1024x16_libGran_8_rw extends MacroCompilerSpec with HasSRAMGener override lazy val libWidth = 8 override lazy val libMaskGran = Some(8) - compile(mem, lib, v, false) - execute(mem, lib, false, output) + compileExecuteAndTest(mem, lib, v, output) } class SplitWidth1024x16_libGran_1_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator { @@ -397,8 +365,7 @@ class SplitWidth1024x16_libGran_1_rw extends MacroCompilerSpec with HasSRAMGener override lazy val libWidth = 8 override lazy val libMaskGran = Some(1) - compile(mem, lib, v, false) - execute(mem, lib, false, output) + compileExecuteAndTest(mem, lib, v, output) } // Non-memMask and non-1 libMask @@ -487,8 +454,7 @@ class SplitWidth1024x32_readEnable_Lib extends MacroCompilerSpec with HasSRAMGen outer_dout <= mux(UInt<1>("h1"), outer_dout_0, UInt<1>("h0")) """ - compile(mem, lib, v, false) - execute(mem, lib, false, output) + compileExecuteAndTest(mem, lib, v, output) } class SplitWidth1024x32_readEnable_Mem extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator { @@ -515,8 +481,7 @@ class SplitWidth1024x32_readEnable_Mem extends MacroCompilerSpec with HasSRAMGen // No need to override body here due to the lack of a readEnable in the lib. - compile(mem, lib, v, false) - execute(mem, lib, false, output) + compileExecuteAndTest(mem, lib, v, output) } class SplitWidth1024x32_readEnable_LibMem extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator { @@ -590,6 +555,5 @@ class SplitWidth1024x32_readEnable_LibMem extends MacroCompilerSpec with HasSRAM outer_dout <= mux(UInt<1>("h1"), outer_dout_0, UInt<1>("h0")) """ - compile(mem, lib, v, false) - execute(mem, lib, false, output) + compileExecuteAndTest(mem, lib, v, output) }