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[FireChip] Use clock in BridgeBinders

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This commit is contained in:
David Biancolin
2019-11-01 17:17:57 -07:00
parent e859fb1779
commit e3b30dbd83
2 changed files with 6 additions and 5 deletions
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10
generators/firechip/src/main/scala/BridgeBinders.scala
View File

@@ -32,19 +32,19 @@ class WithTiedOffDebug extends RegisterBridgeBinder({ case target: HasPeripheryD
}) })
class WithSerialBridge extends RegisterBridgeBinder({ class WithSerialBridge extends RegisterBridgeBinder({
case target: HasPeripherySerialModuleImp => Seq(SerialBridge(target.serial)(target.p)) case target: HasPeripherySerialModuleImp => Seq(SerialBridge(target.clock, target.serial)(target.p))
}) })
class WithNICBridge extends RegisterBridgeBinder({ class WithNICBridge extends RegisterBridgeBinder({
case target: HasPeripheryIceNICModuleImpValidOnly => Seq(NICBridge(target.net)(target.p)) case target: HasPeripheryIceNICModuleImpValidOnly => Seq(NICBridge(target.clock, target.net)(target.p))
}) })
class WithUARTBridge extends RegisterBridgeBinder({ class WithUARTBridge extends RegisterBridgeBinder({
case target: HasPeripheryUARTModuleImp => target.uart.map(u => UARTBridge(u)(target.p)) case target: HasPeripheryUARTModuleImp => target.uart.map(u => UARTBridge(target.clock, u)(target.p))
}) })
class WithBlockDeviceBridge extends RegisterBridgeBinder({ class WithBlockDeviceBridge extends RegisterBridgeBinder({
case target: HasPeripheryBlockDeviceModuleImp => Seq(BlockDevBridge(target.bdev, target.reset.toBool)(target.p)) case target: HasPeripheryBlockDeviceModuleImp => Seq(BlockDevBridge(target.clock ,target.bdev, target.reset.toBool)(target.p))
}) })
class WithFASEDBridge extends RegisterBridgeBinder({ class WithFASEDBridge extends RegisterBridgeBinder({
@@ -55,7 +55,7 @@ class WithFASEDBridge extends RegisterBridgeBinder({
val nastiKey = NastiParameters(axi4Bundle.r.bits.data.getWidth, val nastiKey = NastiParameters(axi4Bundle.r.bits.data.getWidth,
axi4Bundle.ar.bits.addr.getWidth, axi4Bundle.ar.bits.addr.getWidth,
axi4Bundle.ar.bits.id.getWidth) axi4Bundle.ar.bits.id.getWidth)
FASEDBridge(axi4Bundle, t.reset.toBool, FASEDBridge(t.clock, axi4Bundle, t.reset.toBool,
CompleteConfig(p(firesim.configs.MemModelKey), nastiKey, Some(AXI4EdgeSummary(edge)))) CompleteConfig(p(firesim.configs.MemModelKey), nastiKey, Some(AXI4EdgeSummary(edge))))
}) })
}).toSeq }).toSeq

1
generators/firechip/src/main/scala/TargetMixins.scala
View File

@@ -41,6 +41,7 @@ trait HasTraceIOImp extends LazyModuleImp {
(traceIO.traces zip outer.traceNexus.in).foreach({ case (port, (tileTrace, _)) => (traceIO.traces zip outer.traceNexus.in).foreach({ case (port, (tileTrace, _)) =>
port := DeclockedTracedInstruction.fromVec(tileTrace) port := DeclockedTracedInstruction.fromVec(tileTrace)
}) })
traceIO.clock := clock
// Enabled to test TracerV trace capture // Enabled to test TracerV trace capture
if (p(PrintTracePort)) { if (p(PrintTracePort)) {