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Merge pull request #1856 from ucb-bar/freq-fixes

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Automatically set `DTSTimebase` to PBUS frequency
This commit is contained in:
Abraham Gonzalez
2024-04-21 21:02:00 -07:00
committed by GitHub
parent 4ad6d411f0 8c7edaf128
commit e2ddd45cc7
3 changed files with 6 additions and 9 deletions
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2
fpga/src/main/scala/arty/Configs.scala
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@@ -5,7 +5,6 @@ import org.chipsalliance.cde.config._
import freechips.rocketchip.subsystem._ import freechips.rocketchip.subsystem._
import freechips.rocketchip.devices.debug._ import freechips.rocketchip.devices.debug._
import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase}
import freechips.rocketchip.system._ import freechips.rocketchip.system._
import freechips.rocketchip.tile._ import freechips.rocketchip.tile._
@@ -25,7 +24,6 @@ class WithArtyTweaks extends Config(
new chipyard.harness.WithHarnessBinderClockFreqMHz(32) ++ new chipyard.harness.WithHarnessBinderClockFreqMHz(32) ++
new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++ new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++
new chipyard.config.WithDTSTimebase(32000) ++
new chipyard.config.WithSystemBusFrequency(32) ++ new chipyard.config.WithSystemBusFrequency(32) ++
new chipyard.config.WithFrontBusFrequency(32) ++ new chipyard.config.WithFrontBusFrequency(32) ++
new chipyard.config.WithControlBusFrequency(32) ++ new chipyard.config.WithControlBusFrequency(32) ++

9
generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala
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@@ -89,9 +89,12 @@ class WithFbusToSbusCrossingType(xType: ClockCrossingType) extends Config((site,
* Mixins to set the dtsFrequency field of BusParams -- these will percolate its way * Mixins to set the dtsFrequency field of BusParams -- these will percolate its way
* up the diplomatic graph to the clock sources. * up the diplomatic graph to the clock sources.
*/ */
class WithPeripheryBusFrequency(freqMHz: Double) extends Config((site, here, up) => { class WithPeripheryBusFrequency(freqMHz: Double) extends Config(
case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong))) new freechips.rocketchip.subsystem.WithTimebase((freqMHz * 1e3).toLong) ++ // Match DTS timebase to PBUS (i.e. RTC) frequency. Makes RTC 'tick' at the PBUS rate.
}) new Config((site, here, up) => {
case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong)))
})
)
class WithMemoryBusFrequency(freqMHz: Double) extends Config((site, here, up) => { class WithMemoryBusFrequency(freqMHz: Double) extends Config((site, here, up) => {
case MemoryBusKey => up(MemoryBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong))) case MemoryBusKey => up(MemoryBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong)))
}) })

4
generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala
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@@ -18,10 +18,6 @@ class WithSystemBusWidth(bitWidth: Int) extends Config((site, here, up) => {
case SystemBusKey => up(SystemBusKey, site).copy(beatBytes=bitWidth/8) case SystemBusKey => up(SystemBusKey, site).copy(beatBytes=bitWidth/8)
}) })
class WithDTSTimebase(freqMHz: BigInt) extends Config((site, here, up) => {
case DTSTimebase => freqMHz
})
// Adds buffers on the interior of the inclusive LLC, to improve PD // Adds buffers on the interior of the inclusive LLC, to improve PD
class WithInclusiveCacheInteriorBuffer(buffer: InclusiveCachePortParameters = InclusiveCachePortParameters.full) extends Config((site, here, up) => { class WithInclusiveCacheInteriorBuffer(buffer: InclusiveCachePortParameters = InclusiveCachePortParameters.full) extends Config((site, here, up) => {
case InclusiveCacheKey => up(InclusiveCacheKey).copy(bufInnerInterior=buffer, bufOuterInterior=buffer) case InclusiveCacheKey => up(InclusiveCacheKey).copy(bufInnerInterior=buffer, bufOuterInterior=buffer)