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Make SpikeTile ipc a plusarg

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This commit is contained in:
Jerry Zhao
2023-02-04 16:17:02 -08:00
parent b88e583472
commit e27f1a3195
1 changed files with 1 additions and 2 deletions
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3
generators/chipyard/src/main/scala/SpikeTile.scala
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@@ -16,7 +16,6 @@ import freechips.rocketchip.tile._
import freechips.rocketchip.prci.ClockSinkParameters import freechips.rocketchip.prci.ClockSinkParameters
case class SpikeCoreParams( case class SpikeCoreParams(
val maxInsnsPerCycle: Int = 10000
) extends CoreParams { ) extends CoreParams {
val useVM = true val useVM = true
val useHypervisor = false val useHypervisor = false
@@ -305,7 +304,7 @@ class SpikeTileModuleImp(outer: SpikeTile) extends BaseTileModuleImp(outer) {
spike.io.msip := int_bundle.msip spike.io.msip := int_bundle.msip
spike.io.meip := int_bundle.meip spike.io.meip := int_bundle.meip
spike.io.seip := int_bundle.seip.get spike.io.seip := int_bundle.seip.get
spike.io.ipc := outer.spikeTileParams.core.maxInsnsPerCycle.U spike.io.ipc := PlusArg("spike-ipc", 10000, width=64)
val blockBits = log2Ceil(p(CacheBlockBytes)) val blockBits = log2Ceil(p(CacheBlockBytes))
spike.io.icache.a.ready := icache_tl.a.ready spike.io.icache.a.ready := icache_tl.a.ready