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Fix tracegen compile

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This commit is contained in:
abejgonzalez
2022-01-24 14:43:25 -08:00
parent 3a2af96720
commit e17f478d01
1 changed files with 2 additions and 1 deletions
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3
generators/tracegen/src/main/scala/Tile.scala
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@@ -158,7 +158,7 @@ class BoomLSUShim(implicit p: Parameters) extends BoomModule()(p)
io.lsu.rob_head_idx := rob_head io.lsu.rob_head_idx := rob_head
io.tracegen.ordered := ready_for_amo && io.lsu.fencei_rdy
} }
case class BoomTraceGenTileAttachParams( case class BoomTraceGenTileAttachParams(
@@ -236,6 +236,7 @@ class BoomTraceGenTileModuleImp(outer: BoomTraceGenTile)
ptw.io.requestors.head <> lsu.io.ptw ptw.io.requestors.head <> lsu.io.ptw
outer.dcache.module.io.lsu <> lsu.io.dmem outer.dcache.module.io.lsu <> lsu.io.dmem
boom_shim.io.tracegen <> tracegen.io.mem boom_shim.io.tracegen <> tracegen.io.mem
tracegen.io.fence_rdy := boom_shim.io.tracegen.ordered
boom_shim.io.lsu <> lsu.io.core boom_shim.io.lsu <> lsu.io.core
// Normally the PTW would use this port // Normally the PTW would use this port