From 66deeee9a7672be3aa82b105ff9f6931c1668f9f Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 26 Jan 2024 17:52:08 -0800 Subject: [PATCH 01/11] Bump testchipip for improved TLSerdesser --- .../main/scala/config/AbstractConfig.scala | 2 +- .../src/main/scala/config/ChipConfigs.scala | 6 +++--- .../main/scala/config/ChipletConfigs.scala | 4 ++-- .../main/scala/example/FlatTestHarness.scala | 10 +++++----- .../main/scala/harness/HarnessBinders.scala | 20 +++++++++---------- .../scala/harness/MultiHarnessBinders.scala | 14 ++++++------- generators/testchipip | 2 +- 7 files changed, 29 insertions(+), 29 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index 8a328daf..471b4fa0 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -70,7 +70,7 @@ class AbstractConfig extends Config( new testchipip.serdes.WithSerialTL(Seq( // add a serial-tilelink interface testchipip.serdes.SerialTLParams( client = Some(testchipip.serdes.SerialTLClientParams()), // serial-tilelink interface will master the FBUS, and support 4 idBits - phyParams = testchipip.serdes.ExternalSyncSerialParams(width=32) // serial-tilelink interface with 32 lanes + phyParams = testchipip.serdes.ExternalSyncSerialPhyParams(phitWidth=32, flitWidth=32) // serial-tilelink interface with 32 lanes ) )) ++ new testchipip.soc.WithMbusScratchpad(base = 0x08000000, // add 64 KiB on-chip scratchpad diff --git a/generators/chipyard/src/main/scala/config/ChipConfigs.scala b/generators/chipyard/src/main/scala/config/ChipConfigs.scala index 52f39a03..c34492a4 100644 --- a/generators/chipyard/src/main/scala/config/ChipConfigs.scala +++ b/generators/chipyard/src/main/scala/config/ChipConfigs.scala @@ -31,7 +31,7 @@ class ChipLikeRocketConfig extends Config( isMemoryDevice = true )), client = Some(testchipip.serdes.SerialTLClientParams()), // Allow an external manager to probe this chip - phyParams = testchipip.serdes.ExternalSyncSerialParams(width=4) // 4-bit bidir interface, sync'd to an external clock + phyParams = testchipip.serdes.ExternalSyncSerialPhyParams(phitWidth=4, flitWidth=16) // 4-bit bidir interface, sync'd to an external clock ))) ++ new freechips.rocketchip.subsystem.WithNoMemPort ++ // Remove axi4 mem port @@ -77,8 +77,8 @@ class ChipBringupHostConfig extends Config( size = BigInt("80000000", 16) )) )), - client = Some(testchipip.serdes.SerialTLClientParams()), // Allow chip to access this device's memory (DRAM) - phyParams = testchipip.serdes.InternalSyncSerialParams(width=4, freqMHz = 75) // bringup platform provides the clock + client = Some(testchipip.serdes.SerialTLClientParams()), // Allow chip to access this device's memory (DRAM) + phyParams = testchipip.serdes.InternalSyncSerialPhyParams(phitWidth=4, flitWidth=16, freqMHz = 75) // bringup platform provides the clock ))) ++ //============================ diff --git a/generators/chipyard/src/main/scala/config/ChipletConfigs.scala b/generators/chipyard/src/main/scala/config/ChipletConfigs.scala index a7d2113f..56f4b667 100644 --- a/generators/chipyard/src/main/scala/config/ChipletConfigs.scala +++ b/generators/chipyard/src/main/scala/config/ChipletConfigs.scala @@ -16,7 +16,7 @@ class SymmetricChipletRocketConfig extends Config( new testchipip.serdes.WithSerialTL(Seq( testchipip.serdes.SerialTLParams( // 0th serial-tl is chip-to-bringup-fpga client = Some(testchipip.serdes.SerialTLClientParams()), // bringup serial-tl acts only as a client - phyParams = testchipip.serdes.ExternalSyncSerialParams() // bringup serial-tl is sync'd to external clock + phyParams = testchipip.serdes.ExternalSyncSerialPhyParams() // bringup serial-tl is sync'd to external clock ), testchipip.serdes.SerialTLParams( // 1st serial-tl is chip-to-chip client = Some(testchipip.serdes.SerialTLClientParams()), // chip-to-chip serial-tl acts as a client @@ -27,7 +27,7 @@ class SymmetricChipletRocketConfig extends Config( )), slaveWhere = OBUS )), - phyParams = testchipip.serdes.SourceSyncSerialParams() // chip-to-chip serial-tl is symmetric source-sync'd + phyParams = testchipip.serdes.SourceSyncSerialPhyParams() // chip-to-chip serial-tl is symmetric source-sync'd )) ) ++ new testchipip.soc.WithOffchipBusClient(SBUS, // obus provides path to other chip's memory diff --git a/generators/chipyard/src/main/scala/example/FlatTestHarness.scala b/generators/chipyard/src/main/scala/example/FlatTestHarness.scala index 8bbbb205..c97ff84c 100644 --- a/generators/chipyard/src/main/scala/example/FlatTestHarness.scala +++ b/generators/chipyard/src/main/scala/example/FlatTestHarness.scala @@ -47,16 +47,16 @@ class FlatTestHarness(implicit val p: Parameters) extends Module { // Figure out which clock drives the harness TLSerdes, based on the port type val serial_ram_clock = dut.serial_tl_pad match { - case io: InternalSyncSerialIO => io.clock_out - case io: ExternalSyncSerialIO => clock + case io: InternalSyncPhitIO => io.clock_out + case io: ExternalSyncPhitIO => clock } dut.serial_tl_pad match { - case io: ExternalSyncSerialIO => io.clock_in := clock - case io: InternalSyncSerialIO => + case io: ExternalSyncPhitIO => io.clock_in := clock + case io: InternalSyncPhitIO => } dut.serial_tl_pad match { - case pad: DecoupledSerialIO => { + case pad: DecoupledPhitIO => { withClockAndReset(serial_ram_clock, reset) { // SerialRAM implements the memory regions the chip expects val ram = Module(LazyModule(new SerialRAM(lazyDut.system.serdessers(0), p(SerialTLKey)(0))).module) diff --git a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala index 909f1638..d46225ae 100644 --- a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala @@ -209,17 +209,17 @@ class WithTiedOffDMI extends HarnessBinder({ class WithSerialTLTiedOff(tieoffs: Option[Seq[Int]] = None) extends HarnessBinder({ case (th: HasHarnessInstantiators, port: SerialTLPort, chipId: Int) if (tieoffs.map(_.contains(port.portId)).getOrElse(true)) => { port.io match { - case io: DecoupledSerialIO => io.out.ready := false.B; io.in.valid := false.B; io.in.bits := DontCare; - case io: SourceSyncSerialIO => { + case io: DecoupledPhitIO => io.out.ready := false.B; io.in.valid := false.B; io.in.bits := DontCare; + case io: SourceSyncPhitIO => { io.clock_in := false.B.asClock io.reset_in := false.B.asAsyncReset - io.in := DontCare + io.phit_in := DontCare io.credit_in := DontCare } } port.io match { - case io: InternalSyncSerialIO => - case io: ExternalSyncSerialIO => io.clock_in := false.B.asClock + case io: InternalSyncPhitIO => + case io: ExternalSyncPhitIO => io.clock_in := false.B.asClock case _ => } } @@ -228,17 +228,17 @@ class WithSerialTLTiedOff(tieoffs: Option[Seq[Int]] = None) extends HarnessBinde class WithSimTSIOverSerialTL extends HarnessBinder({ case (th: HasHarnessInstantiators, port: SerialTLPort, chipId: Int) if (port.portId == 0) => { port.io match { - case io: InternalSyncSerialIO => - case io: ExternalSyncSerialIO => io.clock_in := th.harnessBinderClock + case io: InternalSyncPhitIO => + case io: ExternalSyncPhitIO => io.clock_in := th.harnessBinderClock } port.io match { - case io: DecoupledSerialIO => { + case io: DecoupledPhitIO => { // If the port is locally synchronous (provides a clock), drive everything with that clock // Else, drive everything with the harnes clock val clock = port.io match { - case io: InternalSyncSerialIO => io.clock_out - case io: ExternalSyncSerialIO => th.harnessBinderClock + case io: InternalSyncPhitIO => io.clock_out + case io: ExternalSyncPhitIO => th.harnessBinderClock } withClock(clock) { val ram = Module(LazyModule(new SerialRAM(port.serdesser, port.params)(port.serdesser.p)).module) diff --git a/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala b/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala index 5da69fc7..94fb18d9 100644 --- a/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala +++ b/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala @@ -59,25 +59,25 @@ class WithMultiChipSerialTL(chip0: Int, chip1: Int, chip0portId: Int = 0, chip1p (p0: SerialTLPort) => p0.portId == chip0portId, (p1: SerialTLPort) => p1.portId == chip1portId, (th: HasHarnessInstantiators, p0: SerialTLPort, p1: SerialTLPort) => { - def connectDecoupledSyncSerialIO(clkSource: InternalSyncSerialIO, clkSink: ExternalSyncSerialIO) = { + def connectDecoupledSyncPhitIO(clkSource: InternalSyncPhitIO, clkSink: ExternalSyncPhitIO) = { clkSink.clock_in := clkSource.clock_out clkSink.in <> clkSource.out clkSource.in <> clkSink.out } - def connectSourceSyncSerialIO(a: SourceSyncSerialIO, b: SourceSyncSerialIO) = { + def connectSourceSyncPhitIO(a: SourceSyncPhitIO, b: SourceSyncPhitIO) = { a.clock_in := b.clock_out b.clock_in := a.clock_out a.reset_in := b.reset_out b.reset_in := a.reset_out - a.in := b.out - b.in := a.out + a.phit_in := b.phit_out + b.phit_in := a.phit_out a.credit_in := b.credit_out b.credit_in := a.credit_out } (p0.io, p1.io) match { - case (io0: InternalSyncSerialIO, io1: ExternalSyncSerialIO) => connectDecoupledSyncSerialIO(io0, io1) - case (io0: ExternalSyncSerialIO, io1: InternalSyncSerialIO) => connectDecoupledSyncSerialIO(io1, io0) - case (io0: SourceSyncSerialIO , io1: SourceSyncSerialIO ) => connectSourceSyncSerialIO (io0, io1) + case (io0: InternalSyncPhitIO, io1: ExternalSyncPhitIO) => connectDecoupledSyncPhitIO(io0, io1) + case (io0: ExternalSyncPhitIO, io1: InternalSyncPhitIO) => connectDecoupledSyncPhitIO(io1, io0) + case (io0: SourceSyncPhitIO , io1: SourceSyncPhitIO ) => connectSourceSyncPhitIO (io0, io1) } } ) diff --git a/generators/testchipip b/generators/testchipip index edacb214..2e9eb79f 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit edacb214f081e5034f131af74efa0ac5f4452ee6 +Subproject commit 2e9eb79f9bc1dc1783e64c3cf187c2c882d585f2 From 205a1f202964f341a76ecee0aa747326ad8e04b0 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 26 Jan 2024 18:39:58 -0800 Subject: [PATCH 02/11] Remove bringup vcu118 --- fpga/src/main/scala/arty100t/Configs.scala | 2 +- .../main/scala/arty100t/HarnessBinders.scala | 26 +-- .../scala/vcu118/bringup/BringupGPIOs.scala | 28 --- .../main/scala/vcu118/bringup/Configs.scala | 97 --------- .../scala/vcu118/bringup/CustomOverlays.scala | 204 ------------------ .../scala/vcu118/bringup/DigitalTop.scala | 26 --- .../scala/vcu118/bringup/HarnessBinders.scala | 51 ----- .../main/scala/vcu118/bringup/IOBinders.scala | 30 --- .../scala/vcu118/bringup/TestHarness.scala | 99 --------- 9 files changed, 14 insertions(+), 549 deletions(-) delete mode 100644 fpga/src/main/scala/vcu118/bringup/BringupGPIOs.scala delete mode 100644 fpga/src/main/scala/vcu118/bringup/Configs.scala delete mode 100644 fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala delete mode 100644 fpga/src/main/scala/vcu118/bringup/DigitalTop.scala delete mode 100644 fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala delete mode 100644 fpga/src/main/scala/vcu118/bringup/IOBinders.scala delete mode 100644 fpga/src/main/scala/vcu118/bringup/TestHarness.scala diff --git a/fpga/src/main/scala/arty100t/Configs.scala b/fpga/src/main/scala/arty100t/Configs.scala index bb4b8e22..f64dbdf3 100644 --- a/fpga/src/main/scala/arty100t/Configs.scala +++ b/fpga/src/main/scala/arty100t/Configs.scala @@ -58,5 +58,5 @@ class NoCoresArty100TConfig extends Config( class BringupArty100TConfig extends Config( new WithArty100TSerialTLToGPIO ++ new WithArty100TTweaks(freqMHz = 50) ++ - new testchipip.serdes.WithSerialTLPHYParams(testchipip.serdes.InternalSyncSerialParams(freqMHz=50)) ++ + new testchipip.serdes.WithSerialTLPHYParams(testchipip.serdes.InternalSyncSerialPhyParams(freqMHz=50)) ++ new chipyard.ChipBringupHostConfig) diff --git a/fpga/src/main/scala/arty100t/HarnessBinders.scala b/fpga/src/main/scala/arty100t/HarnessBinders.scala index 11a99421..c2b89a24 100644 --- a/fpga/src/main/scala/arty100t/HarnessBinders.scala +++ b/fpga/src/main/scala/arty100t/HarnessBinders.scala @@ -61,10 +61,10 @@ class WithArty100TSerialTLToGPIO extends HarnessBinder({ harnessIO <> port.io harnessIO match { - case io: DecoupledSerialIO => { + case io: DecoupledPhitIO => { val clkIO = io match { - case io: InternalSyncSerialIO => IOPin(io.clock_out) - case io: ExternalSyncSerialIO => IOPin(io.clock_in) + case io: InternalSyncPhitIO => IOPin(io.clock_out) + case io: ExternalSyncPhitIO => IOPin(io.clock_in) } val packagePinsWithPackageIOs = Seq( ("G13", clkIO), @@ -72,14 +72,14 @@ class WithArty100TSerialTLToGPIO extends HarnessBinder({ ("A11", IOPin(io.out.ready)), ("D12", IOPin(io.in.valid)), ("D13", IOPin(io.in.ready)), - ("B18", IOPin(io.out.bits, 0)), - ("A18", IOPin(io.out.bits, 1)), - ("K16", IOPin(io.out.bits, 2)), - ("E15", IOPin(io.out.bits, 3)), - ("E16", IOPin(io.in.bits, 0)), - ("D15", IOPin(io.in.bits, 1)), - ("C15", IOPin(io.in.bits, 2)), - ("J17", IOPin(io.in.bits, 3)) + ("B18", IOPin(io.out.bits.phit, 0)), + ("A18", IOPin(io.out.bits.phit, 1)), + ("K16", IOPin(io.out.bits.phit, 2)), + ("E15", IOPin(io.out.bits.phit, 3)), + ("E16", IOPin(io.in.bits.phit, 0)), + ("D15", IOPin(io.in.bits.phit, 1)), + ("C15", IOPin(io.in.bits.phit, 2)), + ("J17", IOPin(io.in.bits.phit, 3)) ) packagePinsWithPackageIOs foreach { case (pin, io) => { artyTh.xdc.addPackagePin(io, pin) @@ -88,10 +88,10 @@ class WithArty100TSerialTLToGPIO extends HarnessBinder({ // Don't add IOB to the clock, if its an input io match { - case io: InternalSyncSerialIO => packagePinsWithPackageIOs foreach { case (pin, io) => { + case io: InternalSyncPhitIO => packagePinsWithPackageIOs foreach { case (pin, io) => { artyTh.xdc.addIOB(io) }} - case io: ExternalSyncSerialIO => packagePinsWithPackageIOs.drop(1).foreach { case (pin, io) => { + case io: ExternalSyncPhitIO => packagePinsWithPackageIOs.drop(1).foreach { case (pin, io) => { artyTh.xdc.addIOB(io) }} } diff --git a/fpga/src/main/scala/vcu118/bringup/BringupGPIOs.scala b/fpga/src/main/scala/vcu118/bringup/BringupGPIOs.scala deleted file mode 100644 index 40c33bfa..00000000 --- a/fpga/src/main/scala/vcu118/bringup/BringupGPIOs.scala +++ /dev/null @@ -1,28 +0,0 @@ -package chipyard.fpga.vcu118.bringup - -import scala.collection.mutable.{LinkedHashMap} - -object BringupGPIOs { - // map of the pin name (akin to die pin name) to (fpga package pin, IOSTANDARD, add pullup resistor?) - val pinMapping = LinkedHashMap( - // these connect to LEDs and switches on the VCU118 (and use 1.2V) - "led0" -> ("AT32", "LVCMOS12", false), // 0 - "led1" -> ("AV34", "LVCMOS12", false), // 1 - "led2" -> ("AY30", "LVCMOS12", false), // 2 - "led3" -> ("BB32", "LVCMOS12", false), // 3 - "led4" -> ("BF32", "LVCMOS12", false), // 4 - "led5" -> ("AU37", "LVCMOS12", false), // 5 - "led6" -> ("AV36", "LVCMOS12", false), // 6 - "led7" -> ("BA37", "LVCMOS12", false), // 7 - "sw0" -> ("B17", "LVCMOS12", false), // 8 - "sw1" -> ("G16", "LVCMOS12", false), // 9 - "sw2" -> ("J16", "LVCMOS12", false), // 10 - "sw3" -> ("D21", "LVCMOS12", false) // 11 - ) - - // return list of names (ordered) - def names: Seq[String] = pinMapping.keys.toSeq - - // return number of GPIOs - def width: Int = pinMapping.size -} diff --git a/fpga/src/main/scala/vcu118/bringup/Configs.scala b/fpga/src/main/scala/vcu118/bringup/Configs.scala deleted file mode 100644 index 0760fa72..00000000 --- a/fpga/src/main/scala/vcu118/bringup/Configs.scala +++ /dev/null @@ -1,97 +0,0 @@ -package chipyard.fpga.vcu118.bringup - -import math.min - -import org.chipsalliance.cde.config.{Config, Parameters} -import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet, ResourceBinding, Resource, ResourceAddress} -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.subsystem.{MasterPortParams} - -import sifive.blocks.devices.gpio.{PeripheryGPIOKey, GPIOParams} -import sifive.blocks.devices.i2c.{PeripheryI2CKey, I2CParams} -import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} - -import sifive.fpgashells.shell.{DesignKey} -import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize} - -import testchipip.tsi.{PeripheryTSIHostKey, TSIHostParams, TSIHostSerdesParams} - -import chipyard.{BuildSystem} - -import chipyard.fpga.vcu118.{WithVCU118Tweaks, WithFPGAFrequency, VCU118DDR2Size} -import chipyard.iobinders.{WithGPIOPunchthrough} - -class WithBringupPeripherals extends Config((site, here, up) => { - case PeripheryUARTKey => up(PeripheryUARTKey, site) ++ List(UARTParams(address = BigInt(0x64003000L))) - case PeripheryI2CKey => List(I2CParams(address = BigInt(0x64005000L))) - case PeripheryGPIOKey => { - if (BringupGPIOs.width > 0) { - require(BringupGPIOs.width <= 64) // currently only support 64 GPIOs (change addrs to get more) - val gpioAddrs = Seq(BigInt(0x64002000), BigInt(0x64007000)) - val maxGPIOSupport = 32 // max gpios supported by SiFive driver (split by 32) - List.tabulate(((BringupGPIOs.width - 1)/maxGPIOSupport) + 1)(n => { - GPIOParams(address = gpioAddrs(n), width = min(BringupGPIOs.width - maxGPIOSupport*n, maxGPIOSupport)) - }) - } - else { - List.empty[GPIOParams] - } - } - case TSIClockMaxFrequencyKey => 100 - case PeripheryTSIHostKey => List( - TSIHostParams( - offchipSerialIfWidth = 4, - mmioBaseAddress = BigInt(0x64006000), - mmioSourceId = 1 << 13, // manager source - serdesParams = TSIHostSerdesParams( - clientPortParams = TLMasterPortParameters.v1( - clients = Seq(TLMasterParameters.v1( - name = "tl-tsi-host-serdes", - sourceId = IdRange(0, (1 << 13))))), - managerPortParams = TLSlavePortParameters.v1( - managers = Seq(TLSlaveParameters.v1( - address = Seq(AddressSet(0, BigInt("FFFFFFFF", 16))), // access everything on chip - regionType = RegionType.UNCACHED, - executable = true, - supportsGet = TransferSizes(1, 64), - supportsPutFull = TransferSizes(1, 64), - supportsPutPartial = TransferSizes(1, 64), - supportsAcquireT = TransferSizes(1, 64), - supportsAcquireB = TransferSizes(1, 64), - supportsArithmetic = TransferSizes(1, 64), - supportsLogical = TransferSizes(1, 64))), - endSinkId = 1 << 6, // manager sink - beatBytes = 8)), - targetMasterPortParams = MasterPortParams( - base = BigInt("80000000", 16), - size = site(VCU118DDR2Size), - beatBytes = 8, // comes from test chip - idBits = 4) // comes from VCU118 idBits in XilinxVCU118MIG - )) -}) - -class WithBringupVCU118System extends Config((site, here, up) => { - case BuildSystem => (p: Parameters) => new BringupVCU118DigitalTop()(p) // use the VCU118-extended bringup digital top -}) - -class WithBringupAdditions extends Config( - new WithBringupUART ++ - new WithBringupI2C ++ - new WithBringupGPIO ++ - new WithBringupTSIHost ++ - new WithTSITLIOPassthrough ++ - new WithGPIOPunchthrough ++ - new WithBringupPeripherals ++ - new WithBringupVCU118System) - -class RocketBringupConfig extends Config( - new WithBringupAdditions ++ - new WithVCU118Tweaks ++ - new chipyard.RocketConfig) - -class BoomBringupConfig extends Config( - new WithFPGAFrequency(50) ++ - new WithBringupAdditions ++ - new WithVCU118Tweaks ++ - new chipyard.MegaBoomConfig) diff --git a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala deleted file mode 100644 index a52a1b5e..00000000 --- a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala +++ /dev/null @@ -1,204 +0,0 @@ -package chipyard.fpga.vcu118.bringup - -import chisel3._ -import chisel3.experimental.{attach} - -import freechips.rocketchip.diplomacy._ -import org.chipsalliance.cde.config.{Parameters, Field} -import freechips.rocketchip.tilelink.{TLInwardNode, TLAsyncCrossingSink} - -import sifive.fpgashells.shell._ -import sifive.fpgashells.ip.xilinx._ -import sifive.fpgashells.shell.xilinx._ -import sifive.fpgashells.clocks._ -import sifive.fpgashells.devices.xilinx.xilinxvcu118mig.{XilinxVCU118MIGPads, XilinxVCU118MIGParams, XilinxVCU118MIG} - -import testchipip.tsi.{TSIHostWidgetIO} - -import chipyard.fpga.vcu118.{FMCPMap} - -/* Connect the I2C to certain FMC pins */ -class BringupI2CVCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name: String, val designInput: I2CDesignInput, val shellInput: I2CShellInput) - extends I2CXilinxPlacedOverlay(name, designInput, shellInput) -{ - shell { InModuleBody { - require(shellInput.index == 0) // only support 1 I2C <-> FMC connection - val i2cLocations = List(List(FMCPMap("K11"), FMCPMap("E2"))) - val packagePinsWithPackageIOs = Seq((i2cLocations(shellInput.index)(0), IOPin(io.scl)), - (i2cLocations(shellInput.index)(1), IOPin(io.sda))) - - packagePinsWithPackageIOs foreach { case (pin, io) => { - shell.xdc.addPackagePin(io, pin) - shell.xdc.addIOStandard(io, "LVCMOS18") - shell.xdc.addIOB(io) - } } - } } -} - -class BringupI2CVCU118ShellPlacer(val shell: VCU118ShellBasicOverlays, val shellInput: I2CShellInput)(implicit val valName: ValName) - extends I2CShellPlacer[VCU118ShellBasicOverlays] -{ - def place(designInput: I2CDesignInput) = new BringupI2CVCU118PlacedOverlay(shell, valName.name, designInput, shellInput) -} - -/* Connect the UART to certain FMC pins */ -class BringupUARTVCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name: String, val designInput: UARTDesignInput, val shellInput: UARTShellInput) - extends UARTXilinxPlacedOverlay(name, designInput, shellInput, true) -{ - shell { InModuleBody { - val packagePinsWithPackageIOs = Seq((FMCPMap("E9"), IOPin(io.ctsn.get)), // unused - (FMCPMap("E10"), IOPin(io.rtsn.get)), // unused - (FMCPMap("C15"), IOPin(io.rxd)), - (FMCPMap("C14"), IOPin(io.txd))) - - packagePinsWithPackageIOs foreach { case (pin, io) => { - shell.xdc.addPackagePin(io, pin) - shell.xdc.addIOStandard(io, "LVCMOS18") - shell.xdc.addIOB(io) - } } - - // add pullup on ctsn (ctsn is an input that is not used or driven) - packagePinsWithPackageIOs take 1 foreach { case (pin, io) => { - shell.xdc.addPullup(io) - } } - } } -} - -class BringupUARTVCU118ShellPlacer(shell: VCU118ShellBasicOverlays, val shellInput: UARTShellInput)(implicit val valName: ValName) - extends UARTShellPlacer[VCU118ShellBasicOverlays] { - def place(designInput: UARTDesignInput) = new BringupUARTVCU118PlacedOverlay(shell, valName.name, designInput, shellInput) -} - -/* Connect GPIOs to FPGA I/Os */ -abstract class GPIOXilinxPlacedOverlay(name: String, di: GPIODesignInput, si: GPIOShellInput) - extends GPIOPlacedOverlay(name, di, si) -{ - def shell: XilinxShell - - shell { InModuleBody { - (io.gpio zip tlgpioSink.bundle.pins).map { case (ioPin, sinkPin) => - val iobuf = Module(new IOBUF) - iobuf.suggestName(s"gpio_iobuf") - attach(ioPin, iobuf.io.IO) - sinkPin.i.ival := iobuf.io.O - iobuf.io.T := !sinkPin.o.oe - iobuf.io.I := sinkPin.o.oval - } - } } -} - -class BringupGPIOVCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name: String, val designInput: GPIODesignInput, val shellInput: GPIOShellInput, gpioNames: Seq[String]) - extends GPIOXilinxPlacedOverlay(name, designInput, shellInput) -{ - shell { InModuleBody { - require(gpioNames.length == io.gpio.length) - - val packagePinsWithIOStdWithPackageIOs = (gpioNames zip io.gpio).map { case (name, io) => - val (pin, iostd, pullupEnable) = BringupGPIOs.pinMapping(name) - (pin, iostd, pullupEnable, IOPin(io)) - } - - packagePinsWithIOStdWithPackageIOs foreach { case (pin, iostd, pullupEnable, io) => { - shell.xdc.addPackagePin(io, pin) - shell.xdc.addIOStandard(io, iostd) - if (iostd == "LVCMOS12") { shell.xdc.addDriveStrength(io, "8") } - if (pullupEnable) { shell.xdc.addPullup(io) } - } } - } } -} - -class BringupGPIOVCU118ShellPlacer(shell: VCU118ShellBasicOverlays, val shellInput: GPIOShellInput, gpioNames: Seq[String])(implicit val valName: ValName) - extends GPIOShellPlacer[VCU118ShellBasicOverlays] { - def place(designInput: GPIODesignInput) = new BringupGPIOVCU118PlacedOverlay(shell, valName.name, designInput, shellInput, gpioNames) -} - -case class TSIHostShellInput() -case class TSIHostDesignInput( - serialIfWidth: Int, - node: BundleBridgeSource[TSIHostWidgetIO] - )( - implicit val p: Parameters) -case class TSIHostOverlayOutput() -trait TSIHostShellPlacer[Shell] extends ShellPlacer[TSIHostDesignInput, TSIHostShellInput, TSIHostOverlayOutput] - -case object TSIHostOverlayKey extends Field[Seq[DesignPlacer[TSIHostDesignInput, TSIHostShellInput, TSIHostOverlayOutput]]](Nil) - -abstract class TSIHostPlacedOverlay[IO <: Data](val name: String, val di: TSIHostDesignInput, val si: TSIHostShellInput) - extends IOPlacedOverlay[IO, TSIHostDesignInput, TSIHostShellInput, TSIHostOverlayOutput] -{ - implicit val p = di.p -} - -case object TSIHostVCU118DDRSize extends Field[BigInt](0x40000000L * 2) // 2GB -class TSIHostVCU118PlacedOverlay(val shell: BringupVCU118FPGATestHarness, name: String, val designInput: TSIHostDesignInput, val shellInput: TSIHostShellInput) - extends TSIHostPlacedOverlay[TSIHostWidgetIO](name, designInput, shellInput) -{ - val tlTsiSerialSink = di.node.makeSink() - val tsiIoNode = BundleBridgeSource(() => new TSIHostWidgetIO(di.serialIfWidth)) - val topTSIIONode = shell { tsiIoNode.makeSink() } - - def overlayOutput = TSIHostOverlayOutput() - def ioFactory = new TSIHostWidgetIO(di.serialIfWidth) - - InModuleBody { - // connect TSI serial - val tsiSourcePort = tsiIoNode.bundle - val tsiSinkPort = tlTsiSerialSink.bundle - tsiSinkPort.serial_clock := tsiSourcePort.serial_clock - tsiSourcePort.serial.out.bits := tsiSinkPort.serial.out.bits - tsiSourcePort.serial.out.valid := tsiSinkPort.serial.out.valid - tsiSinkPort.serial.out.ready := tsiSourcePort.serial.out.ready - tsiSinkPort.serial.in.bits := tsiSourcePort.serial.in.bits - tsiSinkPort.serial.in.valid := tsiSourcePort.serial.in.valid - tsiSourcePort.serial.in.ready := tsiSinkPort.serial.in.ready - } -} - -case object TSIClockMaxFrequencyKey extends Field[Int](50) // in MHz -class BringupTSIHostVCU118PlacedOverlay(override val shell: BringupVCU118FPGATestHarness, override val name: String, override val designInput: TSIHostDesignInput, override val shellInput: TSIHostShellInput) - extends TSIHostVCU118PlacedOverlay(shell, name, designInput, shellInput) -{ - // connect the TSI port - shell { InModuleBody { - // connect TSI signals - val tsiPort = topTSIIONode.bundle - io <> tsiPort - - require(di.serialIfWidth == 4) - - val clkIo = IOPin(io.serial_clock) - val packagePinsWithPackageIOs = Seq( - (FMCPMap("D8"), clkIo), - (FMCPMap("D17"), IOPin(io.serial.out.ready)), - (FMCPMap("D18"), IOPin(io.serial.out.valid)), - (FMCPMap("D11"), IOPin(io.serial.out.bits, 0)), - (FMCPMap("D12"), IOPin(io.serial.out.bits, 1)), - (FMCPMap("D14"), IOPin(io.serial.out.bits, 2)), - (FMCPMap("D15"), IOPin(io.serial.out.bits, 3)), - (FMCPMap("D26"), IOPin(io.serial.in.ready)), - (FMCPMap("D27"), IOPin(io.serial.in.valid)), - (FMCPMap("D20"), IOPin(io.serial.in.bits, 0)), - (FMCPMap("D21"), IOPin(io.serial.in.bits, 1)), - (FMCPMap("D23"), IOPin(io.serial.in.bits, 2)), - (FMCPMap("D24"), IOPin(io.serial.in.bits, 3))) - - packagePinsWithPackageIOs foreach { case (pin, io) => { - shell.xdc.addPackagePin(io, pin) - shell.xdc.addIOStandard(io, "LVCMOS18") - } } - - // Don't add an IOB to the clock - (packagePinsWithPackageIOs take 1) foreach { case (pin, io) => { - shell.xdc.addIOB(io) - } } - - shell.sdc.addClock("TSI_CLK", clkIo, p(TSIClockMaxFrequencyKey)) - shell.sdc.addGroup(pins = Seq(clkIo)) - shell.xdc.clockDedicatedRouteFalse(clkIo) - } } -} - -class BringupTSIHostVCU118ShellPlacer(shell: BringupVCU118FPGATestHarness, val shellInput: TSIHostShellInput)(implicit val valName: ValName) - extends TSIHostShellPlacer[BringupVCU118FPGATestHarness] { - def place(designInput: TSIHostDesignInput) = new BringupTSIHostVCU118PlacedOverlay(shell, valName.name, designInput, shellInput) -} diff --git a/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala b/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala deleted file mode 100644 index e4efbdc7..00000000 --- a/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala +++ /dev/null @@ -1,26 +0,0 @@ -package chipyard.fpga.vcu118.bringup - -import chisel3._ - -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.system._ -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.devices.tilelink._ -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.tilelink._ - -import chipyard.{DigitalTop, DigitalTopModule} - -// ------------------------------------ -// Bringup VCU118 DigitalTop -// ------------------------------------ - -class BringupVCU118DigitalTop(implicit p: Parameters) extends DigitalTop - with sifive.blocks.devices.i2c.HasPeripheryI2C - with testchipip.tsi.HasPeripheryTSIHostWidget -{ - override lazy val module = new BringupVCU118DigitalTopModule(this) -} - -class BringupVCU118DigitalTopModule[+L <: BringupVCU118DigitalTop](l: L) extends DigitalTopModule(l) - with sifive.blocks.devices.i2c.HasPeripheryI2CModuleImp diff --git a/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala b/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala deleted file mode 100644 index 27933bf6..00000000 --- a/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala +++ /dev/null @@ -1,51 +0,0 @@ -package chipyard.fpga.vcu118.bringup - -import chisel3._ -import chisel3.experimental.{Analog, IO, BaseModule} - -import freechips.rocketchip.util.{HeterogeneousBag} -import freechips.rocketchip.tilelink.{TLBundle} - -import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp, UARTPortIO} -import sifive.blocks.devices.spi.{HasPeripherySPI, SPIPortIO} -import sifive.blocks.devices.i2c.{HasPeripheryI2CModuleImp, I2CPort} -import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp, GPIOPortIO} - -import testchipip.tsi.{HasPeripheryTSIHostWidget, TSIHostWidgetIO} - -import chipyard.harness._ -import chipyard.iobinders._ - -/*** UART ***/ -class WithBringupUART extends HarnessBinder({ - case (th: BringupVCU118FPGATestHarnessImp, port: UARTPort, chipId: Int) => { - th.bringupOuter.io_fmc_uart_bb.bundle <> port.io - } -}) - -/*** I2C ***/ -class WithBringupI2C extends HarnessBinder({ - case (th: BringupVCU118FPGATestHarnessImp, port: chipyard.iobinders.I2CPort, chipId: Int) => { - th.bringupOuter.io_i2c_bb.bundle <> port.io - } -}) - -/*** GPIO ***/ -class WithBringupGPIO extends HarnessBinder({ - case (th: BringupVCU118FPGATestHarnessImp, port: GPIOPort, chipId: Int) => { - th.bringupOuter.io_gpio_bb(port.pinId).bundle <> port.io - } -}) - -/*** TSI Host Widget ***/ -class WithBringupTSIHost extends HarnessBinder({ - case (th: BringupVCU118FPGATestHarnessImp, port: TLMemPort, chipId: Int) => { - val tsiBundles = th.bringupOuter.tsiDdrClient.out.map(_._1) - val tsiDdrClientBundle = Wire(new HeterogeneousBag(tsiBundles.map(_.cloneType))) - tsiBundles.zip(tsiDdrClientBundle).foreach { case (bundle, io) => bundle <> io } - tsiDdrClientBundle <> port.io - } - case (th: BringupVCU118FPGATestHarnessImp, port: TSIHostWidgetPort, chipId: Int) => { - th.bringupOuter.io_tsi_serial_bb.bundle <> port.io - } -}) diff --git a/fpga/src/main/scala/vcu118/bringup/IOBinders.scala b/fpga/src/main/scala/vcu118/bringup/IOBinders.scala deleted file mode 100644 index c80f828e..00000000 --- a/fpga/src/main/scala/vcu118/bringup/IOBinders.scala +++ /dev/null @@ -1,30 +0,0 @@ -package chipyard.fpga.vcu118.bringup - -import chisel3._ -import chisel3.reflect.DataMirror - -import freechips.rocketchip.util.{HeterogeneousBag} -import freechips.rocketchip.tilelink.{TLBundle} - -import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp} -import sifive.blocks.devices.i2c.{HasPeripheryI2CModuleImp} - -import testchipip.tsi.{HasPeripheryTSIHostWidget, TSIHostWidgetIO} - -import chipyard.iobinders.{OverrideIOBinder, Port, TLMemPort} - -case class TSIHostWidgetPort(val getIO: () => TSIHostWidgetIO) - extends Port[TSIHostWidgetIO] - -class WithTSITLIOPassthrough extends OverrideIOBinder({ - (system: HasPeripheryTSIHostWidget) => { - require(system.tsiTLMem.size == 1) - val io_tsi_tl_mem_pins_temp = IO(DataMirror.internal.chiselTypeClone[HeterogeneousBag[TLBundle]](system.tsiTLMem.head)).suggestName("tsi_tl_slave") - io_tsi_tl_mem_pins_temp <> system.tsiTLMem.head - - require(system.tsiSerial.size == 1) - val io_tsi_serial_pins_temp = IO(DataMirror.internal.chiselTypeClone[TSIHostWidgetIO](system.tsiSerial.head)).suggestName("tsi_serial") - io_tsi_serial_pins_temp <> system.tsiSerial.head - (Seq(TLMemPort(() => io_tsi_tl_mem_pins_temp), TSIHostWidgetPort(() => io_tsi_serial_pins_temp)), Nil) - } -}) diff --git a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala deleted file mode 100644 index 3de1e595..00000000 --- a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala +++ /dev/null @@ -1,99 +0,0 @@ -package chipyard.fpga.vcu118.bringup -import chisel3._ - -import freechips.rocketchip.diplomacy._ -import org.chipsalliance.cde.config._ -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.prci._ -import sifive.fpgashells.shell.xilinx._ -import sifive.fpgashells.ip.xilinx._ -import sifive.fpgashells.shell._ -import sifive.fpgashells.clocks._ - -import sifive.blocks.devices.uart._ -import sifive.blocks.devices.spi._ -import sifive.blocks.devices.i2c._ -import sifive.blocks.devices.gpio._ - -import testchipip.tsi.{HasPeripheryTSIHostWidget, PeripheryTSIHostKey, TSIHostWidgetIO} -import testchipip.util.{TLSinkSetter} - -import chipyard.fpga.vcu118.{VCU118FPGATestHarness, VCU118FPGATestHarnessImp, DDR2VCU118ShellPlacer, SysClock2VCU118ShellPlacer} - -import chipyard.{ChipTop} -import chipyard.harness._ - -class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118FPGATestHarness { - - /*** UART ***/ - - require(dp(PeripheryUARTKey).size == 2) - - // 2nd UART goes to the FMC UART - - val uart_fmc = Overlay(UARTOverlayKey, new BringupUARTVCU118ShellPlacer(this, UARTShellInput())) - - val io_fmc_uart_bb = BundleBridgeSource(() => (new UARTPortIO(dp(PeripheryUARTKey).last))) - dp(UARTOverlayKey).last.place(UARTDesignInput(io_fmc_uart_bb)) - - /*** I2C ***/ - - val i2c = Overlay(I2COverlayKey, new BringupI2CVCU118ShellPlacer(this, I2CShellInput())) - - val io_i2c_bb = BundleBridgeSource(() => (new I2CPort)) - dp(I2COverlayKey).head.place(I2CDesignInput(io_i2c_bb)) - - /*** GPIO ***/ - - val gpio = Seq.tabulate(dp(PeripheryGPIOKey).size)(i => { - val maxGPIOSupport = 32 // max gpio per gpio chip - val names = BringupGPIOs.names.slice(maxGPIOSupport*i, maxGPIOSupport*(i+1)) - Overlay(GPIOOverlayKey, new BringupGPIOVCU118ShellPlacer(this, GPIOShellInput(), names)) - }) - - val io_gpio_bb = dp(PeripheryGPIOKey).map { p => BundleBridgeSource(() => (new GPIOPortIO(p))) } - (dp(GPIOOverlayKey) zip dp(PeripheryGPIOKey)).zipWithIndex.map { case ((placer, params), i) => - placer.place(GPIODesignInput(params, io_gpio_bb(i))) - } - - /*** TSI Host Widget ***/ - require(dp(PeripheryTSIHostKey).size == 1) - - // use the 2nd system clock for the 2nd DDR - val sysClk2Node = dp(ClockInputOverlayKey).last.place(ClockInputDesignInput()).overlayOutput.node - - val ddr2PLL = dp(PLLFactoryKey)() - ddr2PLL := sysClk2Node - - val ddr2Clock = ClockSinkNode(freqMHz = dp(FPGAFrequencyKey)) - val ddr2Wrangler = LazyModule(new ResetWrangler) - val ddr2Group = ClockGroup() - ddr2Clock := ddr2Wrangler.node := ddr2Group := ddr2PLL - - val tsi_host = Overlay(TSIHostOverlayKey, new BringupTSIHostVCU118ShellPlacer(this, TSIHostShellInput())) - - val ddr2Node = dp(DDROverlayKey).last.place(DDRDesignInput(dp(PeripheryTSIHostKey).head.targetMasterPortParams.base, ddr2Wrangler.node, ddr2PLL)).overlayOutput.ddr - - val io_tsi_serial_bb = BundleBridgeSource(() => (new TSIHostWidgetIO(dp(PeripheryTSIHostKey).head.offchipSerialIfWidth))) - dp(TSIHostOverlayKey).head.place(TSIHostDesignInput(dp(PeripheryTSIHostKey).head.offchipSerialIfWidth, io_tsi_serial_bb)) - - // connect 1 mem. channel to the FPGA DDR - val tsiDdrClient = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1( - name = "chip_ddr", - sourceId = IdRange(0, 64) - ))))) - (ddr2Node - := TLFragmenter(8,64,holdFirstDeny=true) - := TLCacheCork() - := TLAtomicAutomata(passthrough=false) - := TLSinkSetter(64) - := tsiDdrClient) - - // module implementation - override lazy val module = new BringupVCU118FPGATestHarnessImp(this) -} - -class BringupVCU118FPGATestHarnessImp(_outer: BringupVCU118FPGATestHarness) extends VCU118FPGATestHarnessImp(_outer) { - lazy val bringupOuter = _outer -} From bf010668e3f2e53d8c40fa66301d820c78fd1e37 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 26 Jan 2024 18:40:08 -0800 Subject: [PATCH 03/11] Bump firechip --- generators/firechip/src/main/scala/BridgeBinders.scala | 4 ++-- generators/firechip/src/main/scala/TargetConfigs.scala | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index bd662a27..55089358 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -15,7 +15,7 @@ import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters} import freechips.rocketchip.util.{ResetCatchAndSync} import sifive.blocks.devices.uart._ -import testchipip.serdes.{ExternalSyncSerialIO} +import testchipip.serdes.{ExternalSyncPhitIO} import testchipip.tsi.{SerialRAM} import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly} @@ -69,7 +69,7 @@ class WithFireSimIOCellModels extends Config((site, here, up) => { class WithTSIBridgeAndHarnessRAMOverSerialTL extends HarnessBinder({ case (th: FireSim, port: SerialTLPort, chipId: Int) => { port.io match { - case io: ExternalSyncSerialIO => { + case io: ExternalSyncPhitIO => { io.clock_in := th.harnessBinderClock val ram = Module(LazyModule(new SerialRAM(port.serdesser, port.params)(port.serdesser.p)).module) ram.io.ser.in <> io.out diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 04bb26a4..ee70de6c 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -265,7 +265,7 @@ class FireSimSmallSystemConfig extends Config( new freechips.rocketchip.subsystem.WithExtMemSize(1 << 28) ++ new testchipip.serdes.WithSerialTL(Seq(testchipip.serdes.SerialTLParams( client = Some(testchipip.serdes.SerialTLClientParams(idBits = 4)), - phyParams = testchipip.serdes.ExternalSyncSerialParams(width=32) + phyParams = testchipip.serdes.ExternalSyncSerialPhyParams(phitWidth=32, flitWidth=32) ))) ++ new testchipip.iceblk.WithBlockDevice ++ new chipyard.config.WithUARTInitBaudRate(BigInt(3686400L)) ++ From 107c1e2c23a25b4c9a3b6ec6e430a52c069295a4 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sat, 27 Jan 2024 00:42:51 -0800 Subject: [PATCH 04/11] Bump testchipip --- generators/testchipip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/testchipip b/generators/testchipip index 2e9eb79f..ec83e5eb 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 2e9eb79f9bc1dc1783e64c3cf187c2c882d585f2 +Subproject commit ec83e5eb9247b2ce2dde9beaa55a2168ac6caf14 From f7790c8bee3aac016bbe9569d1dd8b0fda2ac5e1 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sat, 27 Jan 2024 19:49:42 -0800 Subject: [PATCH 05/11] Bump testchipip --- fpga/Makefile | 14 -------------- .../src/main/scala/harness/HarnessBinders.scala | 3 +-- .../main/scala/harness/MultiHarnessBinders.scala | 6 ++---- generators/testchipip | 2 +- 4 files changed, 4 insertions(+), 21 deletions(-) diff --git a/fpga/Makefile b/fpga/Makefile index a4d3bf99..ebf55a97 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -44,20 +44,6 @@ ifeq ($(SUB_PROJECT),vcu118) FPGA_BRAND ?= xilinx endif -ifeq ($(SUB_PROJECT),bringup) - SBT_PROJECT ?= fpga_platforms - MODEL ?= BringupVCU118FPGATestHarness - VLOG_MODEL ?= BringupVCU118FPGATestHarness - MODEL_PACKAGE ?= chipyard.fpga.vcu118.bringup - CONFIG ?= RocketBringupConfig - CONFIG_PACKAGE ?= chipyard.fpga.vcu118.bringup - GENERATOR_PACKAGE ?= chipyard - TB ?= none # unused - TOP ?= ChipTop - BOARD ?= vcu118 - FPGA_BRAND ?= xilinx -endif - ifeq ($(SUB_PROJECT),nexysvideo) SBT_PROJECT ?= fpga_platforms MODEL ?= NexysVideoHarness diff --git a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala index d46225ae..74d2e4ac 100644 --- a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala @@ -213,8 +213,7 @@ class WithSerialTLTiedOff(tieoffs: Option[Seq[Int]] = None) extends HarnessBinde case io: SourceSyncPhitIO => { io.clock_in := false.B.asClock io.reset_in := false.B.asAsyncReset - io.phit_in := DontCare - io.credit_in := DontCare + io.in := DontCare } } port.io match { diff --git a/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala b/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala index 94fb18d9..55ff4191 100644 --- a/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala +++ b/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala @@ -69,10 +69,8 @@ class WithMultiChipSerialTL(chip0: Int, chip1: Int, chip0portId: Int = 0, chip1p b.clock_in := a.clock_out a.reset_in := b.reset_out b.reset_in := a.reset_out - a.phit_in := b.phit_out - b.phit_in := a.phit_out - a.credit_in := b.credit_out - b.credit_in := a.credit_out + a.in := b.out + b.in := a.out } (p0.io, p1.io) match { case (io0: InternalSyncPhitIO, io1: ExternalSyncPhitIO) => connectDecoupledSyncPhitIO(io0, io1) diff --git a/generators/testchipip b/generators/testchipip index ec83e5eb..6ac7976b 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit ec83e5eb9247b2ce2dde9beaa55a2168ac6caf14 +Subproject commit 6ac7976b215ac4c372ffe9528626b504aafb680b From 1e40679a40df594b0261c292ea0d9041f30d9334 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sun, 28 Jan 2024 17:32:45 -0800 Subject: [PATCH 06/11] Make symmetric test clearer --- generators/testchipip | 2 +- tests/symmetric.c | 10 +++++++--- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/generators/testchipip b/generators/testchipip index 6ac7976b..942bdc5a 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 6ac7976b215ac4c372ffe9528626b504aafb680b +Subproject commit 942bdc5a8d2e43472cee20a3d58124f716c33ce7 diff --git a/tests/symmetric.c b/tests/symmetric.c index a6d37627..d9f2917f 100644 --- a/tests/symmetric.c +++ b/tests/symmetric.c @@ -1,5 +1,6 @@ #include #include +#include #include #include "marchid.h" @@ -20,10 +21,13 @@ int main(void) { memcpy(test, dest + OBUS_OFFSET, sizeof(src)); size_t read_end = rdcycle(); - if (memcmp(src, test, sizeof(src))) { - printf("Remote write/read failed\n"); - exit(1); + for (int i = 0; i < sizeof(src); i++) { + if (src[i] != test[i]) { + printf("Remote write/read failed at %p %p %p %x %x\n", src+i, test+i, dest + OBUS_OFFSET + i, src[i], test[i]); + exit(1); + } } + printf("Read %ld bytes in %ld cycles\n", sizeof(src), read_end - read_start); return 0; From 740f4ebbb3e462dac2767f6a7ae0ab9507ab9f80 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 5 Feb 2024 12:00:39 -0800 Subject: [PATCH 07/11] Bump testchipip --- generators/testchipip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/testchipip b/generators/testchipip index 942bdc5a..2c7d15be 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 942bdc5a8d2e43472cee20a3d58124f716c33ce7 +Subproject commit 2c7d15be0389db8fb29a20d5a41bc8658f10f176 From 6bb41fc6f29ceed99579a3ad6d077002d174f622 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sun, 25 Feb 2024 14:58:22 -0800 Subject: [PATCH 08/11] Add coherent chiplet config --- .../main/scala/config/ChipletConfigs.scala | 46 +++++++++++++++++++ .../main/scala/harness/HarnessBinders.scala | 2 + generators/testchipip | 2 +- 3 files changed, 49 insertions(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/config/ChipletConfigs.scala b/generators/chipyard/src/main/scala/config/ChipletConfigs.scala index 56f4b667..dbf3fa0a 100644 --- a/generators/chipyard/src/main/scala/config/ChipletConfigs.scala +++ b/generators/chipyard/src/main/scala/config/ChipletConfigs.scala @@ -45,3 +45,49 @@ class MultiSimSymmetricChipletRocketConfig extends Config( new chipyard.harness.WithMultiChip(0, new SymmetricChipletRocketConfig) ++ new chipyard.harness.WithMultiChip(1, new SymmetricChipletRocketConfig) ) + +// Core-only chiplet config, where the coherent memory is located on the LLC-chiplet +class RocketCoreChipletConfig extends Config( + new testchipip.serdes.WithSerialTL(Seq( + testchipip.serdes.SerialTLParams( + client = Some(testchipip.serdes.SerialTLClientParams()), + phyParams = testchipip.serdes.ExternalSyncSerialPhyParams() // chip-to-chip serial-tl is symmetric source-sync'd + ), + testchipip.serdes.SerialTLParams( + manager = Some(testchipip.serdes.SerialTLManagerParams( + cohParams = Seq(testchipip.serdes.ManagerCOHParams( + address = BigInt("80000000", 16), + size = BigInt("100000000", 16) + )), + slaveWhere = OBUS, + isMemoryDevice = true + )), + phyParams = testchipip.serdes.SourceSyncSerialPhyParams() + ) + )) ++ + new testchipip.soc.WithOffchipBusClient(SBUS) ++ + new testchipip.soc.WithOffchipBus ++ + new testchipip.soc.WithNoScratchpads ++ + new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++ + new freechips.rocketchip.subsystem.WithNoMemPort ++ + new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new chipyard.config.AbstractConfig) + +// LLC-only chiplet +class LLCChipletConfig extends Config( + new chipyard.harness.WithSerialTLTiedOff ++ + new testchipip.serdes.WithSerialTL(Seq(testchipip.serdes.SerialTLParams( // 1st serial-tl is chip-to-chip + client = Some(testchipip.serdes.SerialTLClientParams(supportsProbe=true)), + phyParams = testchipip.serdes.SourceSyncSerialPhyParams() // chip-to-chip serial-tl is symmetric source-sync'd + ))) ++ + new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 4L) ++ + new chipyard.NoCoresConfig +) + +class MultiSimLLCChipletRocketConfig extends Config( + new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ + new chipyard.harness.WithMultiChipSerialTL(chip0=0, chip1=1, chip0portId=1, chip1portId=0) ++ + new chipyard.harness.WithMultiChip(0, new RocketCoreChipletConfig) ++ + new chipyard.harness.WithMultiChip(1, new LLCChipletConfig) +) diff --git a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala index 74d2e4ac..ead97346 100644 --- a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala @@ -219,6 +219,7 @@ class WithSerialTLTiedOff(tieoffs: Option[Seq[Int]] = None) extends HarnessBinde port.io match { case io: InternalSyncPhitIO => case io: ExternalSyncPhitIO => io.clock_in := false.B.asClock + case io: SourceSyncPhitIO => case _ => } } @@ -229,6 +230,7 @@ class WithSimTSIOverSerialTL extends HarnessBinder({ port.io match { case io: InternalSyncPhitIO => case io: ExternalSyncPhitIO => io.clock_in := th.harnessBinderClock + case io: SourceSyncPhitIO => io.clock_in := th.harnessBinderClock; io.reset_in := th.harnessBinderReset } port.io match { diff --git a/generators/testchipip b/generators/testchipip index 2c7d15be..637d91be 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 2c7d15be0389db8fb29a20d5a41bc8658f10f176 +Subproject commit 637d91be7320bdd02c16d873cb3ba0f05ab12e31 From 2f1776fc6ac846392d2cc44bb0ad2c8fa8cab891 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sun, 25 Feb 2024 15:14:44 -0800 Subject: [PATCH 09/11] Add LLCChiplet to CI --- .github/scripts/defaults.sh | 3 ++- .github/scripts/run-tests.sh | 4 ++++ .github/workflows/chipyard-run-tests.yml | 24 +++++++++++++++++++ .../src/main/scala/TargetConfigs.scala | 2 +- 4 files changed, 31 insertions(+), 2 deletions(-) diff --git a/.github/scripts/defaults.sh b/.github/scripts/defaults.sh index ef7453d2..7384916b 100755 --- a/.github/scripts/defaults.sh +++ b/.github/scripts/defaults.sh @@ -29,7 +29,7 @@ REMOTE_COURSIER_CACHE=$REMOTE_WORK_DIR/.coursier-cache # key value store to get the build groups declare -A grouping grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad chipyard-spike chipyard-clone chipyard-prefetchers chipyard-shuttle" -grouping["group-peripherals"]="chipyard-dmirocket chipyard-dmiboom chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals chipyard-chiplike chipyard-tethered chipyard-symmetric" +grouping["group-peripherals"]="chipyard-dmirocket chipyard-dmiboom chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals chipyard-chiplike chipyard-tethered chipyard-symmetric chipyard-llcchiplet" grouping["group-accels"]="chipyard-mempress chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-manymmioaccels chipyard-nvdla chipyard-aes256ecb" grouping["group-constellation"]="chipyard-constellation" grouping["group-tracegen"]="tracegen tracegen-boom" @@ -59,6 +59,7 @@ mapping["chipyard-manyperipherals"]=" CONFIG=ManyPeripheralsRocketConfig EXTRA_S mapping["chipyard-chiplike"]=" CONFIG=ChipLikeRocketConfig MODEL=FlatTestHarness MODEL_PACKAGE=chipyard.example verilog" mapping["chipyard-tethered"]=" CONFIG=VerilatorCITetheredChipLikeRocketConfig" mapping["chipyard-symmetric"]=" CONFIG=MultiSimSymmetricChipletRocketConfig" +mapping["chipyard-llcchiplet"]=" CONFIG=MultiSimLLCChipletRocketConfig" mapping["chipyard-cloneboom"]=" CONFIG=Cloned64MegaBoomConfig verilog" mapping["chipyard-nocores"]=" CONFIG=NoCoresConfig verilog" mapping["tracegen"]=" CONFIG=NonBlockingTraceGenL2Config" diff --git a/.github/scripts/run-tests.sh b/.github/scripts/run-tests.sh index eccc5563..c3dbd862 100755 --- a/.github/scripts/run-tests.sh +++ b/.github/scripts/run-tests.sh @@ -122,6 +122,10 @@ case $1 in make -C $LOCAL_CHIPYARD_DIR/tests run_binary BINARY=$LOCAL_CHIPYARD_DIR/tests/symmetric.riscv LOADMEM=1 ;; + chipyard-llcchiplet) + make -C $LOCAL_CHIPYARD_DIR/tests + run_binary BINARY=$LOCAL_CHIPYARD_DIR/tests/hello.riscv LOADMEM=1 + ;; tracegen) run_tracegen ;; diff --git a/.github/workflows/chipyard-run-tests.yml b/.github/workflows/chipyard-run-tests.yml index f56f279d..750f5bc3 100644 --- a/.github/workflows/chipyard-run-tests.yml +++ b/.github/workflows/chipyard-run-tests.yml @@ -731,6 +731,29 @@ jobs: group-key: "group-peripherals" project-key: "chipyard-symmetric" + chipyard-llcchiplet-run-tests: + name: chipyard-llcchiplet-run-tests + needs: prepare-chipyard-peripherals + runs-on: as4 + steps: + - name: Delete old checkout + run: | + ls -alh . + rm -rf ${{ github.workspace }}/* || true + rm -rf ${{ github.workspace }}/.* || true + ls -alh . + - name: Checkout + uses: actions/checkout@v3 + - name: Git workaround + uses: ./.github/actions/git-workaround + - name: Create conda env + uses: ./.github/actions/create-conda-env + - name: Run tests + uses: ./.github/actions/run-tests + with: + group-key: "group-peripherals" + project-key: "chipyard-llcchiplet" + chipyard-sha3-run-tests: name: chipyard-sha3-run-tests needs: prepare-chipyard-accels @@ -1095,6 +1118,7 @@ jobs: chipyard-manyperipherals-run-tests, chipyard-tethered-run-tests, chipyard-symmetric-run-tests, + chipyard-llcchiplet-run-tests, chipyard-sha3-run-tests, chipyard-gemmini-run-tests, chipyard-manymmioaccels-run-tests, # chipyard-nvdla-run-tests, diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 8c3147d6..6905612e 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -264,7 +264,7 @@ class FireSimSmallSystemConfig extends Config( new WithoutTLMonitors ++ new freechips.rocketchip.subsystem.WithExtMemSize(1 << 28) ++ new testchipip.serdes.WithSerialTL(Seq(testchipip.serdes.SerialTLParams( - client = Some(testchipip.serdes.SerialTLClientParams(idBits = 4)), + client = Some(testchipip.serdes.SerialTLClientParams(totalIdBits = 4)), phyParams = testchipip.serdes.ExternalSyncSerialPhyParams(phitWidth=32, flitWidth=32) ))) ++ new testchipip.iceblk.WithBlockDevice ++ From f2eb261301fc4fa5d48905e9ec66106984da231c Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 26 Feb 2024 13:47:08 -0800 Subject: [PATCH 10/11] Bump testchipip --- generators/testchipip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/testchipip b/generators/testchipip index 637d91be..696de30c 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 637d91be7320bdd02c16d873cb3ba0f05ab12e31 +Subproject commit 696de30c59d935cb34d2b45b9505dd15fc363086 From b7bc9895cbf2ec8746aca030ed2704ab8e5021a6 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 27 Feb 2024 23:53:36 -0800 Subject: [PATCH 11/11] Add old TLSerdes --- generators/chipyard/src/main/scala/DigitalTop.scala | 3 ++- generators/testchipip | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index bd82585b..ae0c8dad 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -19,7 +19,8 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem with testchipip.cosim.CanHaveTraceIO // Enables optionally adding trace IO with testchipip.soc.CanHaveBankedScratchpad // Enables optionally adding a banked scratchpad with testchipip.iceblk.CanHavePeripheryBlockDevice // Enables optionally adding the block device - with testchipip.serdes.CanHavePeripheryTLSerial // Enables optionally adding the backing memory and serial adapter + with testchipip.serdes.CanHavePeripheryTLSerial // Enables optionally adding the tl-serial interface + with testchipip.serdes.old.CanHavePeripheryTLSerial // Enables optionally adding the DEPRECATED tl-serial interface with testchipip.soc.CanHavePeripheryChipIdPin // Enables optional pin to set chip id for multi-chip configs with sifive.blocks.devices.i2c.HasPeripheryI2C // Enables optionally adding the sifive I2C with sifive.blocks.devices.timer.HasPeripheryTimer // Enables optionally adding the timer device diff --git a/generators/testchipip b/generators/testchipip index be9c416d..5d6ec23c 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit be9c416d6a64462a28433a3eee808cf6cfacdd25 +Subproject commit 5d6ec23cd6d60299615700c00021fc5f69f57788