diff --git a/.github/scripts/defaults.sh b/.github/scripts/defaults.sh index ef7453d2..7384916b 100755 --- a/.github/scripts/defaults.sh +++ b/.github/scripts/defaults.sh @@ -29,7 +29,7 @@ REMOTE_COURSIER_CACHE=$REMOTE_WORK_DIR/.coursier-cache # key value store to get the build groups declare -A grouping grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad chipyard-spike chipyard-clone chipyard-prefetchers chipyard-shuttle" -grouping["group-peripherals"]="chipyard-dmirocket chipyard-dmiboom chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals chipyard-chiplike chipyard-tethered chipyard-symmetric" +grouping["group-peripherals"]="chipyard-dmirocket chipyard-dmiboom chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals chipyard-chiplike chipyard-tethered chipyard-symmetric chipyard-llcchiplet" grouping["group-accels"]="chipyard-mempress chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-manymmioaccels chipyard-nvdla chipyard-aes256ecb" grouping["group-constellation"]="chipyard-constellation" grouping["group-tracegen"]="tracegen tracegen-boom" @@ -59,6 +59,7 @@ mapping["chipyard-manyperipherals"]=" CONFIG=ManyPeripheralsRocketConfig EXTRA_S mapping["chipyard-chiplike"]=" CONFIG=ChipLikeRocketConfig MODEL=FlatTestHarness MODEL_PACKAGE=chipyard.example verilog" mapping["chipyard-tethered"]=" CONFIG=VerilatorCITetheredChipLikeRocketConfig" mapping["chipyard-symmetric"]=" CONFIG=MultiSimSymmetricChipletRocketConfig" +mapping["chipyard-llcchiplet"]=" CONFIG=MultiSimLLCChipletRocketConfig" mapping["chipyard-cloneboom"]=" CONFIG=Cloned64MegaBoomConfig verilog" mapping["chipyard-nocores"]=" CONFIG=NoCoresConfig verilog" mapping["tracegen"]=" CONFIG=NonBlockingTraceGenL2Config" diff --git a/.github/scripts/run-tests.sh b/.github/scripts/run-tests.sh index eccc5563..c3dbd862 100755 --- a/.github/scripts/run-tests.sh +++ b/.github/scripts/run-tests.sh @@ -122,6 +122,10 @@ case $1 in make -C $LOCAL_CHIPYARD_DIR/tests run_binary BINARY=$LOCAL_CHIPYARD_DIR/tests/symmetric.riscv LOADMEM=1 ;; + chipyard-llcchiplet) + make -C $LOCAL_CHIPYARD_DIR/tests + run_binary BINARY=$LOCAL_CHIPYARD_DIR/tests/hello.riscv LOADMEM=1 + ;; tracegen) run_tracegen ;; diff --git a/.github/workflows/chipyard-run-tests.yml b/.github/workflows/chipyard-run-tests.yml index f56f279d..750f5bc3 100644 --- a/.github/workflows/chipyard-run-tests.yml +++ b/.github/workflows/chipyard-run-tests.yml @@ -731,6 +731,29 @@ jobs: group-key: "group-peripherals" project-key: "chipyard-symmetric" + chipyard-llcchiplet-run-tests: + name: chipyard-llcchiplet-run-tests + needs: prepare-chipyard-peripherals + runs-on: as4 + steps: + - name: Delete old checkout + run: | + ls -alh . + rm -rf ${{ github.workspace }}/* || true + rm -rf ${{ github.workspace }}/.* || true + ls -alh . + - name: Checkout + uses: actions/checkout@v3 + - name: Git workaround + uses: ./.github/actions/git-workaround + - name: Create conda env + uses: ./.github/actions/create-conda-env + - name: Run tests + uses: ./.github/actions/run-tests + with: + group-key: "group-peripherals" + project-key: "chipyard-llcchiplet" + chipyard-sha3-run-tests: name: chipyard-sha3-run-tests needs: prepare-chipyard-accels @@ -1095,6 +1118,7 @@ jobs: chipyard-manyperipherals-run-tests, chipyard-tethered-run-tests, chipyard-symmetric-run-tests, + chipyard-llcchiplet-run-tests, chipyard-sha3-run-tests, chipyard-gemmini-run-tests, chipyard-manymmioaccels-run-tests, # chipyard-nvdla-run-tests, diff --git a/fpga/src/main/scala/arty100t/Configs.scala b/fpga/src/main/scala/arty100t/Configs.scala index bb4b8e22..f64dbdf3 100644 --- a/fpga/src/main/scala/arty100t/Configs.scala +++ b/fpga/src/main/scala/arty100t/Configs.scala @@ -58,5 +58,5 @@ class NoCoresArty100TConfig extends Config( class BringupArty100TConfig extends Config( new WithArty100TSerialTLToGPIO ++ new WithArty100TTweaks(freqMHz = 50) ++ - new testchipip.serdes.WithSerialTLPHYParams(testchipip.serdes.InternalSyncSerialParams(freqMHz=50)) ++ + new testchipip.serdes.WithSerialTLPHYParams(testchipip.serdes.InternalSyncSerialPhyParams(freqMHz=50)) ++ new chipyard.ChipBringupHostConfig) diff --git a/fpga/src/main/scala/arty100t/HarnessBinders.scala b/fpga/src/main/scala/arty100t/HarnessBinders.scala index 11a99421..c2b89a24 100644 --- a/fpga/src/main/scala/arty100t/HarnessBinders.scala +++ b/fpga/src/main/scala/arty100t/HarnessBinders.scala @@ -61,10 +61,10 @@ class WithArty100TSerialTLToGPIO extends HarnessBinder({ harnessIO <> port.io harnessIO match { - case io: DecoupledSerialIO => { + case io: DecoupledPhitIO => { val clkIO = io match { - case io: InternalSyncSerialIO => IOPin(io.clock_out) - case io: ExternalSyncSerialIO => IOPin(io.clock_in) + case io: InternalSyncPhitIO => IOPin(io.clock_out) + case io: ExternalSyncPhitIO => IOPin(io.clock_in) } val packagePinsWithPackageIOs = Seq( ("G13", clkIO), @@ -72,14 +72,14 @@ class WithArty100TSerialTLToGPIO extends HarnessBinder({ ("A11", IOPin(io.out.ready)), ("D12", IOPin(io.in.valid)), ("D13", IOPin(io.in.ready)), - ("B18", IOPin(io.out.bits, 0)), - ("A18", IOPin(io.out.bits, 1)), - ("K16", IOPin(io.out.bits, 2)), - ("E15", IOPin(io.out.bits, 3)), - ("E16", IOPin(io.in.bits, 0)), - ("D15", IOPin(io.in.bits, 1)), - ("C15", IOPin(io.in.bits, 2)), - ("J17", IOPin(io.in.bits, 3)) + ("B18", IOPin(io.out.bits.phit, 0)), + ("A18", IOPin(io.out.bits.phit, 1)), + ("K16", IOPin(io.out.bits.phit, 2)), + ("E15", IOPin(io.out.bits.phit, 3)), + ("E16", IOPin(io.in.bits.phit, 0)), + ("D15", IOPin(io.in.bits.phit, 1)), + ("C15", IOPin(io.in.bits.phit, 2)), + ("J17", IOPin(io.in.bits.phit, 3)) ) packagePinsWithPackageIOs foreach { case (pin, io) => { artyTh.xdc.addPackagePin(io, pin) @@ -88,10 +88,10 @@ class WithArty100TSerialTLToGPIO extends HarnessBinder({ // Don't add IOB to the clock, if its an input io match { - case io: InternalSyncSerialIO => packagePinsWithPackageIOs foreach { case (pin, io) => { + case io: InternalSyncPhitIO => packagePinsWithPackageIOs foreach { case (pin, io) => { artyTh.xdc.addIOB(io) }} - case io: ExternalSyncSerialIO => packagePinsWithPackageIOs.drop(1).foreach { case (pin, io) => { + case io: ExternalSyncPhitIO => packagePinsWithPackageIOs.drop(1).foreach { case (pin, io) => { artyTh.xdc.addIOB(io) }} } diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index bd82585b..ae0c8dad 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -19,7 +19,8 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem with testchipip.cosim.CanHaveTraceIO // Enables optionally adding trace IO with testchipip.soc.CanHaveBankedScratchpad // Enables optionally adding a banked scratchpad with testchipip.iceblk.CanHavePeripheryBlockDevice // Enables optionally adding the block device - with testchipip.serdes.CanHavePeripheryTLSerial // Enables optionally adding the backing memory and serial adapter + with testchipip.serdes.CanHavePeripheryTLSerial // Enables optionally adding the tl-serial interface + with testchipip.serdes.old.CanHavePeripheryTLSerial // Enables optionally adding the DEPRECATED tl-serial interface with testchipip.soc.CanHavePeripheryChipIdPin // Enables optional pin to set chip id for multi-chip configs with sifive.blocks.devices.i2c.HasPeripheryI2C // Enables optionally adding the sifive I2C with sifive.blocks.devices.timer.HasPeripheryTimer // Enables optionally adding the timer device diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index 84fc3cd3..5ad20661 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -67,8 +67,8 @@ class AbstractConfig extends Config( // External memory section new testchipip.serdes.WithSerialTL(Seq( /** add a serial-tilelink interface */ testchipip.serdes.SerialTLParams( - client = Some(testchipip.serdes.SerialTLClientParams(idBits=4)), /** serial-tilelink interface will master the FBUS, and support 4 idBits */ - phyParams = testchipip.serdes.ExternalSyncSerialParams(width=32) /** serial-tilelink interface with 32 lanes */ + client = Some(testchipip.serdes.SerialTLClientParams(totalIdBits=4)), // serial-tilelink interface will master the FBUS, and support 4 idBits + phyParams = testchipip.serdes.ExternalSyncSerialPhyParams(phitWidth=32, flitWidth=32) // serial-tilelink interface with 32 lanes ) )) ++ new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ /** Default 1 AXI-4 memory channels */ diff --git a/generators/chipyard/src/main/scala/config/ChipConfigs.scala b/generators/chipyard/src/main/scala/config/ChipConfigs.scala index 52f39a03..c34492a4 100644 --- a/generators/chipyard/src/main/scala/config/ChipConfigs.scala +++ b/generators/chipyard/src/main/scala/config/ChipConfigs.scala @@ -31,7 +31,7 @@ class ChipLikeRocketConfig extends Config( isMemoryDevice = true )), client = Some(testchipip.serdes.SerialTLClientParams()), // Allow an external manager to probe this chip - phyParams = testchipip.serdes.ExternalSyncSerialParams(width=4) // 4-bit bidir interface, sync'd to an external clock + phyParams = testchipip.serdes.ExternalSyncSerialPhyParams(phitWidth=4, flitWidth=16) // 4-bit bidir interface, sync'd to an external clock ))) ++ new freechips.rocketchip.subsystem.WithNoMemPort ++ // Remove axi4 mem port @@ -77,8 +77,8 @@ class ChipBringupHostConfig extends Config( size = BigInt("80000000", 16) )) )), - client = Some(testchipip.serdes.SerialTLClientParams()), // Allow chip to access this device's memory (DRAM) - phyParams = testchipip.serdes.InternalSyncSerialParams(width=4, freqMHz = 75) // bringup platform provides the clock + client = Some(testchipip.serdes.SerialTLClientParams()), // Allow chip to access this device's memory (DRAM) + phyParams = testchipip.serdes.InternalSyncSerialPhyParams(phitWidth=4, flitWidth=16, freqMHz = 75) // bringup platform provides the clock ))) ++ //============================ diff --git a/generators/chipyard/src/main/scala/config/ChipletConfigs.scala b/generators/chipyard/src/main/scala/config/ChipletConfigs.scala index a7d2113f..dbf3fa0a 100644 --- a/generators/chipyard/src/main/scala/config/ChipletConfigs.scala +++ b/generators/chipyard/src/main/scala/config/ChipletConfigs.scala @@ -16,7 +16,7 @@ class SymmetricChipletRocketConfig extends Config( new testchipip.serdes.WithSerialTL(Seq( testchipip.serdes.SerialTLParams( // 0th serial-tl is chip-to-bringup-fpga client = Some(testchipip.serdes.SerialTLClientParams()), // bringup serial-tl acts only as a client - phyParams = testchipip.serdes.ExternalSyncSerialParams() // bringup serial-tl is sync'd to external clock + phyParams = testchipip.serdes.ExternalSyncSerialPhyParams() // bringup serial-tl is sync'd to external clock ), testchipip.serdes.SerialTLParams( // 1st serial-tl is chip-to-chip client = Some(testchipip.serdes.SerialTLClientParams()), // chip-to-chip serial-tl acts as a client @@ -27,7 +27,7 @@ class SymmetricChipletRocketConfig extends Config( )), slaveWhere = OBUS )), - phyParams = testchipip.serdes.SourceSyncSerialParams() // chip-to-chip serial-tl is symmetric source-sync'd + phyParams = testchipip.serdes.SourceSyncSerialPhyParams() // chip-to-chip serial-tl is symmetric source-sync'd )) ) ++ new testchipip.soc.WithOffchipBusClient(SBUS, // obus provides path to other chip's memory @@ -45,3 +45,49 @@ class MultiSimSymmetricChipletRocketConfig extends Config( new chipyard.harness.WithMultiChip(0, new SymmetricChipletRocketConfig) ++ new chipyard.harness.WithMultiChip(1, new SymmetricChipletRocketConfig) ) + +// Core-only chiplet config, where the coherent memory is located on the LLC-chiplet +class RocketCoreChipletConfig extends Config( + new testchipip.serdes.WithSerialTL(Seq( + testchipip.serdes.SerialTLParams( + client = Some(testchipip.serdes.SerialTLClientParams()), + phyParams = testchipip.serdes.ExternalSyncSerialPhyParams() // chip-to-chip serial-tl is symmetric source-sync'd + ), + testchipip.serdes.SerialTLParams( + manager = Some(testchipip.serdes.SerialTLManagerParams( + cohParams = Seq(testchipip.serdes.ManagerCOHParams( + address = BigInt("80000000", 16), + size = BigInt("100000000", 16) + )), + slaveWhere = OBUS, + isMemoryDevice = true + )), + phyParams = testchipip.serdes.SourceSyncSerialPhyParams() + ) + )) ++ + new testchipip.soc.WithOffchipBusClient(SBUS) ++ + new testchipip.soc.WithOffchipBus ++ + new testchipip.soc.WithNoScratchpads ++ + new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++ + new freechips.rocketchip.subsystem.WithNoMemPort ++ + new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new chipyard.config.AbstractConfig) + +// LLC-only chiplet +class LLCChipletConfig extends Config( + new chipyard.harness.WithSerialTLTiedOff ++ + new testchipip.serdes.WithSerialTL(Seq(testchipip.serdes.SerialTLParams( // 1st serial-tl is chip-to-chip + client = Some(testchipip.serdes.SerialTLClientParams(supportsProbe=true)), + phyParams = testchipip.serdes.SourceSyncSerialPhyParams() // chip-to-chip serial-tl is symmetric source-sync'd + ))) ++ + new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 4L) ++ + new chipyard.NoCoresConfig +) + +class MultiSimLLCChipletRocketConfig extends Config( + new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ + new chipyard.harness.WithMultiChipSerialTL(chip0=0, chip1=1, chip0portId=1, chip1portId=0) ++ + new chipyard.harness.WithMultiChip(0, new RocketCoreChipletConfig) ++ + new chipyard.harness.WithMultiChip(1, new LLCChipletConfig) +) diff --git a/generators/chipyard/src/main/scala/example/FlatTestHarness.scala b/generators/chipyard/src/main/scala/example/FlatTestHarness.scala index 8bbbb205..c97ff84c 100644 --- a/generators/chipyard/src/main/scala/example/FlatTestHarness.scala +++ b/generators/chipyard/src/main/scala/example/FlatTestHarness.scala @@ -47,16 +47,16 @@ class FlatTestHarness(implicit val p: Parameters) extends Module { // Figure out which clock drives the harness TLSerdes, based on the port type val serial_ram_clock = dut.serial_tl_pad match { - case io: InternalSyncSerialIO => io.clock_out - case io: ExternalSyncSerialIO => clock + case io: InternalSyncPhitIO => io.clock_out + case io: ExternalSyncPhitIO => clock } dut.serial_tl_pad match { - case io: ExternalSyncSerialIO => io.clock_in := clock - case io: InternalSyncSerialIO => + case io: ExternalSyncPhitIO => io.clock_in := clock + case io: InternalSyncPhitIO => } dut.serial_tl_pad match { - case pad: DecoupledSerialIO => { + case pad: DecoupledPhitIO => { withClockAndReset(serial_ram_clock, reset) { // SerialRAM implements the memory regions the chip expects val ram = Module(LazyModule(new SerialRAM(lazyDut.system.serdessers(0), p(SerialTLKey)(0))).module) diff --git a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala index 909f1638..ead97346 100644 --- a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala @@ -209,17 +209,17 @@ class WithTiedOffDMI extends HarnessBinder({ class WithSerialTLTiedOff(tieoffs: Option[Seq[Int]] = None) extends HarnessBinder({ case (th: HasHarnessInstantiators, port: SerialTLPort, chipId: Int) if (tieoffs.map(_.contains(port.portId)).getOrElse(true)) => { port.io match { - case io: DecoupledSerialIO => io.out.ready := false.B; io.in.valid := false.B; io.in.bits := DontCare; - case io: SourceSyncSerialIO => { + case io: DecoupledPhitIO => io.out.ready := false.B; io.in.valid := false.B; io.in.bits := DontCare; + case io: SourceSyncPhitIO => { io.clock_in := false.B.asClock io.reset_in := false.B.asAsyncReset io.in := DontCare - io.credit_in := DontCare } } port.io match { - case io: InternalSyncSerialIO => - case io: ExternalSyncSerialIO => io.clock_in := false.B.asClock + case io: InternalSyncPhitIO => + case io: ExternalSyncPhitIO => io.clock_in := false.B.asClock + case io: SourceSyncPhitIO => case _ => } } @@ -228,17 +228,18 @@ class WithSerialTLTiedOff(tieoffs: Option[Seq[Int]] = None) extends HarnessBinde class WithSimTSIOverSerialTL extends HarnessBinder({ case (th: HasHarnessInstantiators, port: SerialTLPort, chipId: Int) if (port.portId == 0) => { port.io match { - case io: InternalSyncSerialIO => - case io: ExternalSyncSerialIO => io.clock_in := th.harnessBinderClock + case io: InternalSyncPhitIO => + case io: ExternalSyncPhitIO => io.clock_in := th.harnessBinderClock + case io: SourceSyncPhitIO => io.clock_in := th.harnessBinderClock; io.reset_in := th.harnessBinderReset } port.io match { - case io: DecoupledSerialIO => { + case io: DecoupledPhitIO => { // If the port is locally synchronous (provides a clock), drive everything with that clock // Else, drive everything with the harnes clock val clock = port.io match { - case io: InternalSyncSerialIO => io.clock_out - case io: ExternalSyncSerialIO => th.harnessBinderClock + case io: InternalSyncPhitIO => io.clock_out + case io: ExternalSyncPhitIO => th.harnessBinderClock } withClock(clock) { val ram = Module(LazyModule(new SerialRAM(port.serdesser, port.params)(port.serdesser.p)).module) diff --git a/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala b/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala index 5da69fc7..55ff4191 100644 --- a/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala +++ b/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala @@ -59,25 +59,23 @@ class WithMultiChipSerialTL(chip0: Int, chip1: Int, chip0portId: Int = 0, chip1p (p0: SerialTLPort) => p0.portId == chip0portId, (p1: SerialTLPort) => p1.portId == chip1portId, (th: HasHarnessInstantiators, p0: SerialTLPort, p1: SerialTLPort) => { - def connectDecoupledSyncSerialIO(clkSource: InternalSyncSerialIO, clkSink: ExternalSyncSerialIO) = { + def connectDecoupledSyncPhitIO(clkSource: InternalSyncPhitIO, clkSink: ExternalSyncPhitIO) = { clkSink.clock_in := clkSource.clock_out clkSink.in <> clkSource.out clkSource.in <> clkSink.out } - def connectSourceSyncSerialIO(a: SourceSyncSerialIO, b: SourceSyncSerialIO) = { + def connectSourceSyncPhitIO(a: SourceSyncPhitIO, b: SourceSyncPhitIO) = { a.clock_in := b.clock_out b.clock_in := a.clock_out a.reset_in := b.reset_out b.reset_in := a.reset_out a.in := b.out b.in := a.out - a.credit_in := b.credit_out - b.credit_in := a.credit_out } (p0.io, p1.io) match { - case (io0: InternalSyncSerialIO, io1: ExternalSyncSerialIO) => connectDecoupledSyncSerialIO(io0, io1) - case (io0: ExternalSyncSerialIO, io1: InternalSyncSerialIO) => connectDecoupledSyncSerialIO(io1, io0) - case (io0: SourceSyncSerialIO , io1: SourceSyncSerialIO ) => connectSourceSyncSerialIO (io0, io1) + case (io0: InternalSyncPhitIO, io1: ExternalSyncPhitIO) => connectDecoupledSyncPhitIO(io0, io1) + case (io0: ExternalSyncPhitIO, io1: InternalSyncPhitIO) => connectDecoupledSyncPhitIO(io1, io0) + case (io0: SourceSyncPhitIO , io1: SourceSyncPhitIO ) => connectSourceSyncPhitIO (io0, io1) } } ) diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index bd662a27..55089358 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -15,7 +15,7 @@ import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters} import freechips.rocketchip.util.{ResetCatchAndSync} import sifive.blocks.devices.uart._ -import testchipip.serdes.{ExternalSyncSerialIO} +import testchipip.serdes.{ExternalSyncPhitIO} import testchipip.tsi.{SerialRAM} import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly} @@ -69,7 +69,7 @@ class WithFireSimIOCellModels extends Config((site, here, up) => { class WithTSIBridgeAndHarnessRAMOverSerialTL extends HarnessBinder({ case (th: FireSim, port: SerialTLPort, chipId: Int) => { port.io match { - case io: ExternalSyncSerialIO => { + case io: ExternalSyncPhitIO => { io.clock_in := th.harnessBinderClock val ram = Module(LazyModule(new SerialRAM(port.serdesser, port.params)(port.serdesser.p)).module) ram.io.ser.in <> io.out diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 6b41733d..6905612e 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -264,8 +264,8 @@ class FireSimSmallSystemConfig extends Config( new WithoutTLMonitors ++ new freechips.rocketchip.subsystem.WithExtMemSize(1 << 28) ++ new testchipip.serdes.WithSerialTL(Seq(testchipip.serdes.SerialTLParams( - client = Some(testchipip.serdes.SerialTLClientParams(idBits = 4)), - phyParams = testchipip.serdes.ExternalSyncSerialParams(width=32) + client = Some(testchipip.serdes.SerialTLClientParams(totalIdBits = 4)), + phyParams = testchipip.serdes.ExternalSyncSerialPhyParams(phitWidth=32, flitWidth=32) ))) ++ new testchipip.iceblk.WithBlockDevice ++ new chipyard.config.WithUARTInitBaudRate(BigInt(3686400L)) ++ diff --git a/generators/testchipip b/generators/testchipip index bfd2b641..5d6ec23c 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit bfd2b641de701fa61653fde569311e7fdbe7495d +Subproject commit 5d6ec23cd6d60299615700c00021fc5f69f57788 diff --git a/tests/symmetric.c b/tests/symmetric.c index a6d37627..d9f2917f 100644 --- a/tests/symmetric.c +++ b/tests/symmetric.c @@ -1,5 +1,6 @@ #include #include +#include #include #include "marchid.h" @@ -20,10 +21,13 @@ int main(void) { memcpy(test, dest + OBUS_OFFSET, sizeof(src)); size_t read_end = rdcycle(); - if (memcmp(src, test, sizeof(src))) { - printf("Remote write/read failed\n"); - exit(1); + for (int i = 0; i < sizeof(src); i++) { + if (src[i] != test[i]) { + printf("Remote write/read failed at %p %p %p %x %x\n", src+i, test+i, dest + OBUS_OFFSET + i, src[i], test[i]); + exit(1); + } } + printf("Read %ld bytes in %ld cycles\n", sizeof(src), read_end - read_start); return 0;